September 2006
rev 0.5
Switching Characteristics
1
Parameter
F
in
t
D
t
3
t
4
t
5
t
6
t
7
t
PLZ,
t
PHZ
t
PZL,
t
PZH
t
r
t
f
PCS2I2313ANZ
Name
Maximum Operating Frequency
Duty cycle
2,3
= t
2
÷ t
1
Rising Edge Rate
3
Falling Edge Rate
3
Output to Output Skew
3
SDRAM Buffer LH Prop. Delay
3
SDRAM Buffer HL Prop. Delay
3
SDRAM Buffer Enable Delay
3
SDRAM Buffer Disable Delay
Rise Time for SDATA
(Refer Test Circuit for IIC)
Refer figure no.3
Fall Time for SDATA
(Refer Test Circuit for IIC)
Refer figure no.3
3
Test Conditions
Measured at 1.5V
Measured between 0.4V and 2.4V
Measured between 2.4V and 0.4V
All outputs equally loaded
Input edge greater than 1 V/nS
Input edge greater than 1 V/nS
Input edge greater than 1 V/nS
Input edge greater than 1 V/nS
C
L
= 10pF
C
L
= 400pF
C
L
= 10pF
C
L
= 400pF
Min
45.0
1
1
1
1
1
1
6
Typ
50.0
2
2
150
2.7
2.7
3
3
Max
133
55.0
4
4
225
3.5
3.5
5
5
250
Unit
MHz
%
V/nS
V/nS
pS
nS
nS
nS
nS
nS
nS
20
250
Note: 1. All parameters specified with loaded outputs.
2. Duty cycle of input clock is 50%. Rising and falling edge rate is greater than 1V/nS
3. Parameter is guaranteed by design and characterization. Not 100% tested in production.
Test Circuit for SDRAM Enable and Disable Times
S
1
2
*
V
DD
Open
V
SS
V
DD
500Ω
V
I
PULSE
GENERATOR
R
T
D.U.T
500Ω
V
O
C
L
TEST
t
6
/t
7
t
PLZ
/t
PZL
t
PHZ
/t
PZH
S
1
Open
2
*
V
DD
V
SS
Figure 1. Load circuit for Switching times
13 Output, 3.3V SDRAM Buffer for Desktop PCs with 3 DIMMs
Notice: The information in this document is subject to change without notice.
6 of 13
PULSECORE [ PulseCore Semiconductor ]
