September 2006
rev 0.3
PCS2P3805E
Test Circuits and Waveforms
ENABLE
DISABLE
3V
1.5V
0V
INPUT
3V
1.5V
0V
CONTROL
INPUT
tPZL
1.5V
tPLZ
VOH
Package 1
OUTPUT
VOH
OUTPUT
NORMALLY
LOW
1.5V
SWITCH
CLOSED
0.3V
0.3V
tPHZ
tPZH
Package 2
OUTPUT
1.5V
OUTPUT
NORMALLY
HIGH
SWITCH
OPEN
VOH
VOL
1.5V
VOL
tSK(PP)
= | tPLH2
- tPLH1
| or | tPHL2
- tPHL1
Enable and Disable Times
Note: 1. Diagram shown for input Control Enable-LOW and input Control
Note: Part-to- Part Skew is for package and speed grade.
Disable-HIGH
3V
3V
INPUT
INPUT
1.5V
0V
1.5V
0V
tPHL
tPHL
tPLH
tPLH
VOH
VOH
2.0V
0.8V
OUTPUT
OUTPUT
1.5V
VOL
1.5V
VOL
tSK(P) = | tPLH - tPLH
|
tR
tF
Pulse Skew
Propagation Delay
3.3V CMOS Dual 1-To-5 Clock Driver
7 of 11
Notice: The information in this document is subject to change without notice.
PULSECORE [ PulseCore Semiconductor ]
