January 2007
rev 0.3
Pin Configuration (6L TSOT- 26 Package)
PCS3P7100A
CLKIN
VSS
ModOUT
1
2
3
6
VDD
SS2%
SS1%
PCS3P7100A
5
4
Pin Description
Pin#
1
2
3
4
5
6
Pin Name
CLKIN
VSS
ModOUT
SS1%
SS2%
VDD
Type
I
I
O
I
I
P
Ground to entire chip
Modulated Frequency Output
Description
External Reference Input frequency.
Spread Deviation Selection Pin -1. Refer to “Spread Deviation Selection Table”
for details. Has an Internal pull-up resistor.
Spread Deviation Selection Pin -2. Refer to “Spread Deviation Selection Table”
for details. Has an Internal pull-up resistor.
Power to entire chip
Spread Deviation Selection Table
SS2% Pin
L
L
H
H
SS1% Pin
L
H
L
H
Spread Deviation @ 55MHz
± 1.50%
± 1.25%
± 0.75%
± 1.00%
Custom Clock Generator for Display Systems
Notice: The information in this document is subject to change without notice.
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PULSECORE [ PulseCore Semiconductor ]
