November 2006
rev 0.3
Z
0
=50
Ω
Z
0
=50
Ω
PCS5I9658
Differential
Pulse Generator
Z=50
Ω
R
T
=50
Ω
R
T
=50
Ω
V
TT
V
TT
Figure 9. PCLK PCS5I958 AC test reference
V
CC
V
CC
÷2
GND
V
CC
V
CC
÷2
t
SK(O)
GND
The pin-to-pin skew is defined as the worst case
difference in propagation delay between any similar
delay path within a single device
Figure 10. Output–to–Output Skew t
SK(O)
PCLK
PCLK
V
PP
= 0.8V
V
CMR
=
V
CC
– 1.3V
V
CC
V
CC
÷2
FB_IN
t
(PD)
GND
Figure 11. Propagation Delay (t
(PD)
). Static phase offset
test reference
3.3V 1:10 LVCMOS PLL Clock Generator
Notice: The information in this document is subject to change without notice.
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