November 2006
rev 0.3
Low Voltage Zero Delay Buffer
Features
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Fully Integrated PLL
Up to 200MHz I/O Frequency
LVCMOS Outputs
Outputs Disable in High Impedance
LVPECL Reference Clock Options
LQFP Packaging
±50pS Cycle–Cycle Jitter
150pS Output Skews
PCS5I961P
reference clock while the PCS5I961P offers an LVPECL
reference clock.
When pulled high the OE pin will force all of the outputs
(except QFB) into a high impedance state. Because the OE
pin does not affect the QFB output, down stream clocks
can be disabled without the internal PLL losing lock.
The PCS5I961P is fully 2.5V or 3.3V compatible and
requires no external loop filter components. All control
inputs accept LVCMOS compatible levels and the outputs
provide low impedance LVCMOS outputs capable of
driving terminated 50Ω transmission lines. For series
terminated lines the PCS5I961P can drive two lines per
output giving the device an effective fanout of 1:36. The
device is packaged in a 32 lead LQFP package to provide
the
optimum
combination
of
board
density
and
performance.
Functional Description
The PCS5I961P is a 2.5V or 3.3V compatible, 1:18 PLL
based zero delay buffer. With output frequencies of up to
200MHz, output skews of 150pS the device meets the
needs of the most demanding clock tree applications.
The PCS5I961P is offered with two different input
configurations.
The
PCS5I961P
offers
an
LVCMOS
Block Diagram
V
CC
PCLK
PCLK
50K
Ref
PLL
0
1
Q0
Q1
Q2
Q3
50K 50K
FB
50K
100-200 MHz
50-100 MHz
FB_IN
F_RANGE
50K
Q14
Q15
Q16
OE
50K
QFB
Figure 1. PCS5I961P Logic Diagram
PulseCore Semiconductor Corporation
1715 S. Bascom Ave Suite 200, Campbell, CA 95008
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Tel: 408-879-9077
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Fax: 408-879-9018
www.pulsecoresemi.com
Notice: The information in this document is subject to change without notice.
PULSECORE [ PulseCore Semiconductor ]
