November 2006
rev 0.3
Table 2: Function Table
Control
REF_SEL
PLL_EN
OE#
FB_SEL
SELA
SELB
SELC
SELD
PCS5I9350
Default
0
1
0
0
0
0
0
0
0
Xtal
Bypass mode, PLL disabled. The
input clock connects to the output
dividers
Outputs enabled
Feedback divider ÷32
÷2 (Bank A)
÷4 (Bank B)
÷4 (Bank C)
÷4 (Bank D)
1
TCLK
PLL enabled. The VCO output connects to
the output dividers
Outputs disabled (three-state)
Feedback divider ÷16
÷ 4 (Bank A)
÷ 8 (Bank B)
÷ 8 (Bank C)
÷ 8 (Bank D)
Absolute Maximum Ratings
Parameter
VDD
VDD
V
IN
V
OUT
V
TT
LU
R
PS
T
S
T
A
T
J
Ø
JC
Ø
JA
ESD
H
FIT
Description
DC Supply Voltage
DC Operating Voltage
DC Input Voltage
DC Output Voltage
Output termination Voltage
Latch Up Immunity
Power Supply Ripple
Temperature, Storage
Temperature, Operating Ambient
Temperature, Junction
Dissipation, Junction to Case
Dissipation, Junction to Ambient
ESD Protection (Human Body Model)
Failure in Time
Condition
Functional
Relative to V
SS
Relative to V
SS
Functional
Ripple Frequency < 100 kHz
Non-functional
Functional
Functional
Functional
Functional
Min
–0.3
2.375
–0.3
–0.3
200
Max
5.5
3.465
VDD+ 0.3
VDD+ 0.3
V
DD
÷2
150
Unit
V
V
V
V
V
mA
mVp-p
°C
°C
°C
°C/W
°C/W
Volts
ppm
–65
–40
+150
+85
+150
42
105
2000
Manufacturing test
10
3.3V 1:10 LVCMOS PLL Clock Generator
Notice: The information in this document is subject to change without notice.
4 of 12
PULSECORE [ PulseCore Semiconductor ]
