November 2006
rev 0.3
Low Voltage Zero Delay Buffer
Features
Fully Integrated PLL
Up to 200MHz I/O Frequency
LVCMOS Outputs
Outputs Disable in High Impedance
LVCMOS Reference Clock Options
LQFP and TQFP Packaging
±50pS Cycle-Cycle Jitter
150pS Output Skews
The
PCS5I961
is
The
offered
with
PCS5I961C
two
offers
different
an
input
configurations.
reference clock.
PCS5I961C
LVCMOS
reference clock while the PCS5I961P offers an LVPECL
When pulled high the OE pin will force all of the outputs
(except QFB) into a high impedance state. Because the OE
pin does not affect the QFB output, down stream clocks
can be disabled without the internal PLL losing lock.
The PCS5I961C is fully 2.5V or 3.3V compatible and
requires no external loop filter components. All control
inputs accept LVCMOS compatible levels and the outputs
provide low impedance LVCMOS outputs capable of
driving terminated 50Ω transmission lines. For series
terminated lines the PCS5I961C can drive two lines per
output giving the device an effective fanout of 1:36. The
device is packaged in a 32 lead LQFP and TQFP
Packages.
Functional Description
The PCS5I961C is a 2.5V or 3.3V compatible, 1:18 PLL
based zero delay buffer. With output frequencies of up to
200MHz, output skews of 150pS the device meets the
needs of the most demanding clock tree applications.
Block Diagram
Q0
CCLK
50K
FB_IN
50K
F_RANGE
50K
Q14
Q15
Q16
OE
50K
Figure 1. PCS5I961C Logic Diagram
PLL
Ref
100-200 MHz
FB
50-100 MHz
Q1
0
1
Q2
Q3
QFB
PulseCore Semiconductor Corporation
1715 S. Bascom Ave Suite 200, Campbell, CA 95008
•
Tel: 408-879-9077
•
Fax: 408-879-9018
www.pulsecoresemi.com
Notice: The information in this document is subject to change without notice.
PULSECORE [ PulseCore Semiconductor ]
