欢迎访问ic37.com |
会员登录 免费注册
发布采购

PCS5I9775G-52-ER 参数 Datasheet PDF下载

PCS5I9775G-52-ER图片预览
型号: PCS5I9775G-52-ER
PDF下载: 下载PDF文件 查看货源
内容描述: 2.5V或3.3V , 200MHz的, 14输出零延迟缓冲器 [2.5V or 3.3V, 200MHz, 14 Output Zero Delay Buffer]
分类和应用: 时钟驱动器逻辑集成电路
文件页数/大小: 12 页 / 503 K
品牌: PULSECORE [ PulseCore Semiconductor ]
 浏览型号PCS5I9775G-52-ER的Datasheet PDF文件第2页浏览型号PCS5I9775G-52-ER的Datasheet PDF文件第3页浏览型号PCS5I9775G-52-ER的Datasheet PDF文件第4页浏览型号PCS5I9775G-52-ER的Datasheet PDF文件第5页浏览型号PCS5I9775G-52-ER的Datasheet PDF文件第6页浏览型号PCS5I9775G-52-ER的Datasheet PDF文件第7页浏览型号PCS5I9775G-52-ER的Datasheet PDF文件第8页浏览型号PCS5I9775G-52-ER的Datasheet PDF文件第9页  
September 2006
rev 0.4
2.5V or 3.3V, 200MHz, 14 Output Zero Delay Buffer
General Features
Output frequency range: 8.3MHz to 200MHz
Input frequency range: 4.2MHz to 125MHz
2.5V or 3.3V operation
Split 2.5V/3.3V outputs
14 Clock outputs: Drive up to 28 clock lines
1 Feedback clock output
2 LVCMOS reference clock inputs
150pS max output-output skew
PLL bypass mode
‘SpreadTrak’
Output enable/disable
Industrial temperature range: -40°C to +85°C
52 Pin 1.0 mm TQFP Package
RoHS Compliance
PCS5I9775
provides 14 outputs partitioned in 3 banks of 5, 5, and 4
outputs. Bank A and Bank B divide the VCO output by 4
or 8 while Bank C divides by 8 or 12 per SEL(A:C)
settings, see
Functional Table.
These dividers allow
output to input ratios of 6:1, 4:1, 3:1, 2:1, 3:2, 4:3, 1:1,
and 2:3. Each LVCMOS compatible output can drive 50Ω
series or parallel terminated transmission lines. For series
terminated transmission lines, each output can drive one
or two traces giving the device an effective fanout of 1:28.
The PLL is ensured stable, given that the VCO is
configured to run between 200MHz and 500MHz. This
allows a wide range of output frequencies from 8.3MHz to
200MHz. For normal operation, the external feedback
input, FB_IN, is connected to the feedback output,
FB_OUT. The internal VCO is running at multiples of the
input reference clock set by the feedback divider, see
Frequency Table.
When PLL_EN is LOW, PLL is
bypassed and the reference clock directly feeds the
output dividers. This mode is fully static and the minimum
input clock frequency specification does not apply.
Functional Description
The PCS5I9775 is a low-voltage high-performance
200MHz PLL-based zero delay buffer designed for
high-speed
clock
distribution
applications.
The
PCS5I9775 features two reference clock inputs and
Block Diagram
.
VCO_SEL (1, 0)
PLL_EN
TCLK_SEL
TCLK0
TCLK1
FB_IN
SELA
÷2/÷4
CLK
STOP
÷2
PLL
200-
500MHZ
÷2/÷4
÷4
CLK
STOP
QA0
QA1
QA2
QA3
QA4
QB0
QB1
QB2
QB3
QB4
SELB
÷4/÷6
SELC
CLK_STP#
CLK
STOP
QC0
QC1
QC2
QC3
FB_OUT
÷4/÷6/÷8/÷12
FB_SEL(1.0)
MR#/OE
PulseCore Semiconductor Corporation
1715 S. Bascom Ave Suite 200, Campbell, CA 95008
Tel: 408-879-9077
Fax: 408-879-9018
www.pulsecoresemi.com
Notice: The information in this document is subject to change without notice.