May 2007
rev 0.2
Switching Characteristics for PCS5P23Z05B and PCS5P23Z09B
Parameter
1/t
1
t
3
t
4
t
5
t
6
t
7
t
J
t
LOCK
PCS5P23Z05B/09B
Description
Output Frequency
Duty Cycle
2
= (t
2
/ t
1
) * 100
Output Rise Time
1, 2
Output Fall Time
1, 2
Output-to-output skew
2
Delay, CLKIN Rising Edge to
CLKOUT Rising Edge
2
Test Conditions
30pF load
Measured at V
DD
/2
Measured between 0.8V and 2.0V
Measured between 2.0V and 0.8V
All outputs equally loaded
Measured at V
DD
/2
Measured at V
DD
/2 on the CLKOUT pins
of the device
Loaded outputs
Stable power supply, valid clock presented
on CLKIN pin
Min
20
40
Typ
50
Max
50
60
2.5
2.5
250
±350
700
200
1.0
Unit
MHz
%
nS
nS
pS
pS
pS
pS
mS
Device-to-Device Skew
2
Cycle-to-cycle jitter
2
PLL Lock Time
2
Note: 1. The parameters are specified with loaded outputs.
2. Parameter is guaranteed by design and characterization. Not 100% tested in production
Timing-Safe™ Peak EMI Reduction IC
Notice: The information in this document is subject to change without notice.
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PULSECORE [ PulseCore Semiconductor ]
