May 2007
rev 0.2
PCS5P23Z05D
PCS5P23Z09D
Multiple Output Timing-Safe™ Peak EMI reduction IC
General Features
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the REF pin. The PLL feedback is on-chip and is obtained
from the CLKOUT pad.
The PCS5P23Z09D has two banks of four outputs each,
which can be controlled by the Select inputs as shown in
the Select Input Decoding Table. The select input also
allows the input clock to be directly applied to the outputs
for chip and system testing purposes.
Multiple PCS5P23Z05D/09D devices can accept the same
input clock and distribute it. In this case the skew between
the outputs of the two devices is guaranteed to be less than
700pS.
All outputs have less than 200pS of cycle-to-cycle jitter.
The input and output propagation delay is guaranteed to be
less than ±350pS, and the output to output skew is
guaranteed to be less than 250pS.
Refer
“
Spread Spectrum Control and Input-Output Skew
Table”
for
deviations
and
Input-Output
skew
for
PCS5P23Z05D and PCS5P23Z09D devices.
The PCS5P23Z05D/09D is available in two different
packages, as shown in the ordering information table.
Input frequency range: 100MHz to 150MHz
Clock distribution with Timing-Safe™ Peak EMI
Reduction
Zero input - output propagation delay
Multiple low-skew outputs
Output-output skew less than 250pS
Device-device skew less than 700pS
One input drives 9 outputs, grouped as
4 + 4 + 1(PCS5P23Z09D)
One input drives 5 outputs (PCS5P23Z05D)
Less than 200 pS cycle-to-cycle jitter is compatible
with Pentium based systems
Available in 16pin 150-mil SOIC, 4.4 mm TSSOP
(PCS5P23Z09D), and in 8pin 150-mil SOIC,
4.4mm TSSOP package (PCS5P23Z05D)
®
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3.3V operation
Advanced CMOS technology
The First True Drop-in Solution
Functional Description
PCS5P23Z05D/09D is a versatile, 3.3V zero-delay buffer
designed to distribute high-speed Timing-Safe™ clocks
with Peak EMI reduction. PCS5P23Z09D accepts one
reference input and drives out nine low-skew clocks. It is
available in a 16-pin package. The PCS5P23Z05D is the
eight-pin version of the PCS5P23Z09D. It accepts one
reference input and drives out five low-skew clocks.
All parts have on-chip PLLs that lock to an input clock on
Block Diagram
PLL
REF
PLL
CLKOUT
CLK1
CLKA3
CLK2
CLK3
CLKA4
S2
CLK4
S1
Select Input
Decoding
CLKB1
CLKB2
CLKB3
REF
MUX
CLKOUT
CLKA1
CLKA2
PCS5P23Z05D
PCS5P23Z09D
CLKB4
PulseCore Semiconductor Corporation
1715 S. Bascom Ave Suite 200, Campbell, CA 95008
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Tel: 408-879-9077
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Fax: 408-879-9018
www.pulsecoresemi.com
Notice: The information in this document is subject to change without notice.
PULSECORE [ PulseCore Semiconductor ]
