PACE1750A
SIGNAL PROPAGATION DELAYS
1,2
(continued)
15 Mhz
20 MHz
Min
Max
30 MHz
Min
Max
40 MHz
Min
Max
Unit
Symbol
Parameter
IB
0
-IB
15
SNEW
TRIGO RST
Min
Max
t
FC(IBD)V
t
C(SNW)
t
FC(TGO)
t
C(DME)
t
FC(NPU)
t
C(ER)
t
RSTL(NPU)
t
REQV(C)
t
C(REQ)X
t
FV(BB)H
t
BBH(F)X
t
IRV(C)
t
C(IR)X
45
45
45
45
45
45
75
65
0
10
5
5
0
10
30
30
5
5
5
0
10
5
5
0
10
25
30
30
30
40
40
40
60
50
0
10
5
5
0
10
20
22
5
5
25
26
26
35
35
35
50
40
0
10
5
5
0
10
15
17
5
5
20
22
22
30
30
30
45
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
RSTL(DMA ENL)
DMA enable
DMA enable
Normal power up
Clock to major error unrecoverable
RESET
Console request
Console request
Level sensitive faults
Level sensitive faults
IOL
1-2
INT user interrupt (0-5)
Power down interrupt level sensitive
hold
t
RSTL
(t
RSTH
)
Reset pulse width
t
C(XX)Z
t
f(F)
, t
1(1)
t
r
, t
f
Clock to three-state
Edge sensitiive pulse width
Clock rise and fall
13
5
ns
ns
ns
Notes
1. 4.5V
≤
V
CC
≤
5.5V, –55°C
≤
T
C
≤
+125°C. Unless otherwise specified, testing shall be conducted at worst-case conditions.
2. All timing parameters are composed of Three elements. The first "t" stands for timing. The second represents the "from" signal. The third in
parentheses indicates "to" signal. When the CPU clock is one of the signal elements, either the rising edge "C" or the falling edge "FC" is referenced.
When other elements are used, an additional suffix indicates the final logic level of the signal. "L" - low level, "H" - high level, "V" - valid, "Z" - high
impedance, "X" - don't care, "LH" - low to high, "ZH" - high impedance to high, "R" - read cycle, and "W" - write cycle.
Document #
MICRO-3
Rev. C
Page 5 of 24
PYRAMID [ PYRAMID SEMICONDUCTOR CORPORATION ]
