PACE1750AE
TERMINAL CONNECTIONS
Case Outline: Pin Grid Array (Case Z)
Terminal
Number
Terminal
Symbol
Terminal
Number
Terminal
Symbol
Terminal
Number
Terminal
Symbol
B1
B2
C1
C2
D1
D2
E1
E2
F1
F2
G1
G2
H1
H2
J1
V
L5
DMA EN
D11
D10
C11
C10
B11
A10
B10
A9
AS
AS
AS
CC
1
2
3
IB
IB
IB
IB
IB
IB
IB
K5
CON REQ
14
13
12
11
10
9
L6
V
CC
K6
SNEW
BUS LOCK
BUS GNT
BUS BUSY
M/IO
IOL INT
2
L7
V
CC
K7
GND
IOL INT
L8
1
K8
USR INT
5
8
GND
L9
D/I
B9
USR INT
4
IB
IB
IB
IB
IB
IB
IB
IB
K9
R/W
A8
USR INT
3
7
6
5
4
3
2
1
0
L10
K11
K10
J11
J10
H11
H10
G11
G10
F11
F10
E11
E10
GND
B8
USR INT
2
RDYD
A7
USR INT
1
RDYA
B7
USR INT
0
BUS REQ
STRBD
STRBA
CPU CLK
A6
PWRDN INT
GND
B6
J2
A5
MAJ ER
K1
L2
K2
L3
K3
L4
K4
B5
SYSFLT
SYSFLT
1
GND
AK
AK
AK
AK
A4
0
1
2
3
0
UNRCV ER
TIMER CLK
NML PWRUP
RESET
B4
EXT ADR ER
MEM PAR ER
MEM PRT ER
A3
B3
GND
AS
A2
IB
15
TRIGO RST
0
Do c um e nt # MICRO-2 REV G
Pa g e 16 o f 25
PYRAMID [ PYRAMID SEMICONDUCTOR CORPORATION ]
