PACE1750AE
DIFFERENCES BETWEEN THE PACE1750A AND PACE1750AE
The PACE1750AE achieves a 41% boost in performance (in clock cycles) over the PACE1750A. This reduction in clocks
per instruction is because of three architectural enhancements:
1) The inclusion of a 24 x 24 Multiply Accumulate (MAC) array.
2) A reduction in non-bus cycles to 2 clocks (bus cycles remain at 4 clocks to maintain full compatibility with CPU’s
peripheral chips).
3) Branch calculation logic.
The table below shows how the MAC improves all multiply operations — both integer and floating point — by 477% to
760%.
PACE1750AE
Instruction
Integer Add/Sub
Double Precision Integer Add/Sub
Integer Multiply
Double Precision Integer Add/Sub
Floating Add/Sub
Extended Floating Add/Sub
Floating Multiply
Extended Floating Point Multiply
Branch (Taken)
Branch (Not Taken)
Flt’g’ Point Polynomial Step (Mul+Add/Sub)
Ext Flt’g’ Point Polynomial Step (Mul/Sub)
DAIS Mix (MIPS)
Clocks
4
6
4
9
18
34
9
17
8
4
27
51
—
Execution
Time (40 MHz)
100ns
150ns
100ns
225ns
450ns
850ns
225ns
425ns
200ns
100ns
675ns
1275ns
3.56
PACE1750A
Clocks
4
9
23
69
28
51
43
96
12
4
71
147
—
Execution
Gain
Time (40 MHz) #Clocks (%)
100ns
225ns
575ns
1725ns
700ns
1225ns
1075ns
2400ns
300ns
100ns
1775ns
3675ns
2.52
—
50
575
760
55
50
477
564
50
—
263
2400
41/59
PACE1750AE BUILT IN FUNCTIONS
A core set of additional instructions have been included in the PACE1750AE. These instructions utilize the Built ln Function
(BlF) opcode space. The objective of these new opcodes is to enhance the performance of the PACE in critical application
areas such as navigation, DSP, transcendentals and other LINPAK and matrix type instructions. Below is a list of the BlFs
and their execution times (N = the number of elements in the vector being processed).
Instruction
Memory Parametric Dot Product—Single
Memory Parametric Dot Product—Double
3 x 3 Register Dot Product
Double Precision Multiply Accumulate
Polynomial
Clear Accumulator
Store Accumulator (32-Bit)
Store Accumulator (48-Bit)
Load Accumulator (32-Bit)
Load Accumulator Long (48-Bit)
Move MMU Page Block
Load Timer A Reset Register
Load Timer B Reset Register
Mnemonic
VDPS
VDPD
R3DP
MACD
POLY
CLAC
STA
STAL
LAC
LACL
MMPG
LTAR
LTBR
Address
Mode
4F3(RA)
4F1(RA)
4F03
4F02
4F06
4F00
4F08
4F04
4F05
4F07
4F0F
4F0D
4F0E
Number of
Clocks
10 + 8 • N
10+16 • N
6
8
7•N-2
4
7
11
9
9
16+8 • N
4
4
Privileged
Notes
Interruptable
Interruptable
Document #
MICRO-2
REV G
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