PACE1753
AC ELECTRICAL CHARACTERISTICS
(V
CC
= 4.5V)
20 MHz
Symbol
TD/I (EXT ADR)
V
Parameter
MMU Cache Hit
Min
Max
25
25
25
35
25
30
25
25
25
25
35
35
35
35
30
30
34
50
25
25
25
50
40
45
25
32
30MHz
Min
Max
23
20
20
30
20
25
20
20
22
20
25
25
25
25
25
28
30
45
20
22
22
45
35
35
20
30
40 MHz
Min
Max
23
16
19
25
12
23
12
12
18
16
18
18
18
18
17
25
25
40
16
18
18
40
30
30
20
23
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TSTRBD (EXT
ADR ERR)
L
External Address Error
TC (IBD CORR)
IBD
V
(SING ERR)
H
TC (SING ERR)
L
TIBD
V
(EDC GEN)
V
TSTRBD (EX RDY)
L
TC (EX RDY)
H
TC (WR
PROT)
L
TSTRBD
H
(WR
PROT)
H
TC (GNT1)
H
TC (GNT0)
L
TC (GNT0)
H
TC (GNT1)
L
TC (RDYA)
TFC (IB OUT)
V
TIBD
IN
(MEM
PAR ERR)
TC (MEM
PRT ERR)
TSTRBD (WR
PROT)
TC (WR
PROT)
L
TSTRBD
H
(WR
PROT)
H
TD/I (PROT FLAG)
TD/I (PROT FLAG)
TC (PROT FLAG)
TC (PROT FLAG)
TC (EXT ADR)
Error Correction Read Cycle
Error Correction Read Cycle
Error Correction Read Cycle
EDAC or Parity Write Cycle
MMU Cache Miss
MMU Cache Miss
MMU Cache Miss
MMU Cache Miss
Arbiter LOW to HIGH Priority
Arbiter LOW to HIGH Priority
Arbiter HIGH to LOW Priority
Arbiter HIGH to LOW Priority
Address Ready
Clock to IB Out Valid (I/O Read)
Parity Mode
Memory Protect Error
Write Protect Cache Hit
Write Protect Cache Miss
Write Protect Cache Miss
Cache Hit (BPU Protection Error)
Cache Hit (MMU Key-Lock Error)
Cache Miss (BPU Protection Error)
Cache Hit (MMU Key-Lock Error)
Clock to EXT ADR Valid (Miss)
Notes:
1. 4.5V
≤
V
CC
≤
5.5V, –55°C
≤
T
C
≤
+125°C. Unless otherwise specified, testing shall be conducted at worst-case conditions.
2. V
IL
= –3.0V for pulse widths less than or equal to 20ns.
3. Duration of the short should not exceed one second; only one output may be shorted at a time.
4. Pulse width of
WR PROT/PROT
FLAG shall be
≥
80% of
STRBD
pulse width.
Document #
MICRO-4
REV D
Page 4 of 21
PYRAMID [ PYRAMID SEMICONDUCTOR CORPORATION ]
