PACE1754
RDYD Timing
TEST END Timing
1
Notes:
1. The last two instructions executed during system test are: XIO RA, 1F44, 0 and JC 7, 0000 hex, 0. After execution of the
IOW
bus cycle, the
XIO proceeds by filling the instruction pipe with two memory read bus cycles where the opcode 7070 hex and 0000 hex are entered to the
processor. As from the end of
STRBD
in the second cycle, TEST END is asserted. At this point, the execution of IC starts by first issuing two
fetch cycles from the "old PC" (from addresses XXXX & XXXX+1). The data will be taken from system memory (because TEST END is
asserted) but both the address and data are irrelevent. Following that, IC will start filling the pipe from address 0000 hex and 0001 hex, now
from the system memory to start user's program execution.
2. All time measurements on active signals relate to 1.5V levels.
Document #
MICRO-5
REV C
Page 9 of 20
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