P3C1011
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input Timing Reference Level
Output Timing Reference Level
Output Load
V
SS
to 3.0V
3ns
1.5V
1.5V
See Figures 1 and 2
Figure 1. Output Load
* including scope and test fixture.
Note:
Because of the ultra-high speed of the P3C1041, care must be taken
when testing this device; an inadequate setup can cause a normal
functioning part to be rejected as faulty. Long high-inductance leads
that cause supply bounce must be avoided by bringing the V
CC
and
ground planes directly up to the contactor fingers. A 0.01 µF high
frequency capacitor is also required between V
CC
and ground. To avoid
Figure 2. Thevenin Equivalent
signal reflections, proper termination must be used; for example, a 50Ω
test environment should be terminated into a 50Ω load with 1.73V
(Thevenin Voltage) at the comparator input, and a 116Ω resistor must
be used in series with D
OUT
to match 166Ω (Thevenin Resistance).
TRUTH TABLE
Mode
Power-down
Read All Bits
Read Lower Bits Only
Read Upper Bits Only
Write All Bits
Write Lower Bits Only
Write Upper Bits Only
Selected, Outputs Disabled
CE
H
L
L
L
L
L
L
L
O E W E BLE BHE
X
L
L
L
X
X
X
H
X
H
H
H
L
L
L
H
X
L
L
H
L
L
H
X
X
L
H
L
L
H
L
X
I/O
0
- I/O
7
High Z
D
OUT
D
OUT
High Z
D
IN
D
IN
High Z
High Z
I/O
8
- I/O
15
High Z
D
OUT
High Z
D
OUT
D
IN
High Z
D
IN
High Z
Power
Standby
Active
Active
Active
Active
Active
Active
Active
Document #
SRAM131
REV OR
Page 7 of 10
PYRAMID [ PYRAMID SEMICONDUCTOR CORPORATION ]
