P3C1011
HIGH SPEED 128K x 16 (2 MEG)
STATIC CMOS RAM
FEATURES
High Speed (Equal Access and Cycle Times)
— 10/12/15/20 ns (Commercial)
— 12/15/20 ns (Industrial)
— 20/25/35 (Military)
Low Power
— 360 mW (max.)
Single 3.3V ± 0.3V Power Supply
2.0V Data Retention
Easy Memory Expansion Using
CE
and
OE
Inputs
Fully TTL Compatible Inputs and Outputs
Advanced CMOS Technology
Fast t
OE
Automatic Power Down when deselected
Packages
—44-Pin SOJ, TSOP II
DESCRIPTION
The P3C1011 is a 131,072 words by 16 bits high-speed
CMOS static RAM. The CMOS memory requires no
clocks or refreshing, and has equal access and cycle
times. Inputs are fully TTL-compatible. The RAM oper-
ates from a single 3.3V ± 0.3V tolerance power
supply.
Access times as fast as 10 nanoseconds permit greatly
enhanced system operating speeds. CMOS is utilized
to reduce power consumption to a low level. The P3C1011
is a member of a family of PACE RAM™ products offer-
ing fast access times.
The P3C1011 device provides asynchronous operation
with matching access and cycle times. Memory loca-
tions are specified on address pins A
0
to A
17
. Reading is
accomplished by device selection (CE and output en-
abling (OE) while write enable (WE) remains HIGH. By
presenting the address under these conditions, the data
in the addressed memory location is presented on the
data input/output pins. The input/output pins stay in the
HIGH Z state when either
CE
or
OE
is HIGH or
WE
is
LOW.
For both reading and writing, the Byte Enable control lines
(BLE for I/O
0-7
and
BHE
for I/O
8-15
) allow for the selection
of only 8 of the 16 I/O lines if desired. When a Byte
Enable control line is HIGH, the corresponding I/Os are
active.
Package options for the P3C1011 include 44-pin SOJ and
TSOP packages.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
1519B
SOJ
TSOP II
Document #
SRAM131
REV OR
Revised March 2006
1
PYRAMID [ PYRAMID SEMICONDUCTOR CORPORATION ]
