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P3C1024L70SC 参数 Datasheet PDF下载

P3C1024L70SC图片预览
型号: P3C1024L70SC
PDF下载: 下载PDF文件 查看货源
内容描述: 超低功耗128K ×8 CMOS静态RAM [ULTRA LOW POWER 128K x 8 CMOS STATIC RAM]
分类和应用: 存储内存集成电路静态存储器
文件页数/大小: 10 页 / 114 K
品牌: PYRAMID [ PYRAMID SEMICONDUCTOR CORPORATION ]
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P3C1024L
ULTRA LOW POWER 128K x 8
CMOS STATIC RAM
FEATURES
V
CC
Current (Commercial/Industrial)
— Operating: 10mA/12mA
— CMOS Standby: 10µA/10µA
Access Times
—55/70 (Commercial or Industrial)
Single 3.3 Volts ± 0.3V Power Supply
Easy Memory Expansion Using
CE
1,
CE
2
and
OE
Inputs
Common Data I/O
Three-State Outputs
Fully TTL Compatible Inputs and Outputs
Advanced CMOS Technology
Automatic Power Down
Packages
—32-Pin 445 mil SOP
—32-Pin TSOP
DESCRIPTION
The P3C1024L is a 1,048,576-bit low power CMOS static
RAM organized as 128Kx8. The CMOS memory re-
quires no clocks or refreshing, and has equal access
and cycle times. Inputs are fully TTL-compatible. The
RAM operates from a single 3.3V ± 0.3V tolerance power
supply.
Access times of 55 ns and 70 ns are availale. CMOS is
utilized to reduce power consumption to a low level.
The P3C1024L device provides asynchronous opera-
tion with matching access and cycle times. Memory
locations are specified on address pins A
0
to A
16
. Read-
ing is accomplished by device selection (CE
1
low and
CE
2
high) and output enabling (OE) while write enable
(WE) remains HIGH. By presenting the address under
these conditions, the data in the addressed memory lo-
cation is presented on the data input/output pins. The
input/output pins stay in the HIGH Z state when either
CE
1
or
OE
is HIGH or
WE
or CE
2
is LOW.
The P3C1024L is packaged in a 32-pin TSOP and 445
mil SOP.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
SOP (S12)
TOP VIEW
See end of datasheet for TSOP pin configuration.
Document #
SRAM132
REV OR
Revised April 2006
1