P3C1041
AC TEST CONDITIONS
InputPulseLevels
GND to 3.0V
Input Rise and Fall Times
InputTimingReferenceLevel
OutputTimingReferenceLevel
OutputLoad
3ns
1.5V
1.5V
See Figures 1 and 2
Figure 1. Output Load
Figure2. TheveninEquivalent
* including scope and test fixture.
Note:
Because of the ultra-high speed of the P3C1041, care must be taken
when testing this device; an inadequate setup can cause a normal
functioning part to be rejected as faulty. Long high-inductance leads
that cause supply bounce must be avoided by bringing the VCC and
ground planes directly up to the contactor fingers. A 0.01 µF high
frequency capacitor is also required between VCC and ground. To avoid
signal reflections, proper termination must be used; for example, a 50Ω
test environment should be terminated into a 50Ω load with 1.73V
(Thevenin Voltage) at the comparator input, and a 116Ω resistor must
be used in series with DOUT to match 166Ω (Thevenin Resistance).
TRUTH TABLE
CE OE W E BLE BHE I/O0 - I/O7
I/O8 - I/O15
High Z
DOUT
Power
Standby
Active
Active
Active
Mode
H
L
X
L
X
H
X
L
X
L
High Z
DOUT
Power-down
Read All Bits
L
L
L
L
H
H
L
H
L
DOUT
High Z
DOUT
Read Lower Bits Only
Read Upper Bits Only
Write All Bits
H
High Z
L
L
L
L
X
X
X
H
L
L
L
L
L
H
L
DIN
DIN
DIN
High Z
DIN
Active
Active
Active
Active
Write Lower Bits Only
L
H
H
X
High Z
High Z
Write Upper Bits Only
Selected, Outputs Disabled
X
High Z
Document # SRAM130 REV OR
Page 7 of 10
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