P3C1256
HIGH SPEED 32K x 8
3.3V STATIC CMOS RAM
FEATURES
3.3V Power Supply
High Speed (Equal Access and Cycle Times)
— 12/15/20/25 ns (Commercial)
— 15/20/25 ns (Industrial)
Low Power
Single 3.3 Volts ±0.3Volts Power Supply
Easy Memory Expansion Using
CE
and
OE
Inputs
Common Data I/O
Three-State Outputs
Fully TTL Compatible Inputs and Outputs
Advanced CMOS Technology
Automatic Power Down
Packages
—28-Pin TSOP and SOJ
DESCRIPTION
The P3C1256 is a 262,144-bit high-speed CMOS
static RAM organized as 32Kx8. The CMOS memory
requires no clocks or refreshing, and has equal access
and cycle times. Inputs are fully TTL-compatible. The
RAM operates from a single 3.3V± 0.3V tolerance power
supply.
Access times as fast as 12 nanoseconds permit greatly
enhanced system operating speeds. CMOS is utilized
to reduce power consumption to a low level. The
P3C1256 is a member of a family of PACE RAM™ prod-
ucts offering fast access times.
The P3C1256 device provides asynchronous operation
with matching access and cycle times. Memory loca-
tions are specified on address pins A
0
to A
14
. Reading is
accomplished by device selection (CE and output en-
abling (OE) while write enable (WE) remains HIGH. By
presenting the address under these conditions, the data
in the addressed memory location is presented on the
data input/output pins. The input/output pins stay in the
HIGH Z state when either
CE
or
OE
is HIGH or
WE
is
LOW.
Package options for the P3C1256 include 28-pin TSOP
and SOJ packages.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATIONS
SOJ (J5)
1519B
TOP VIEW
See end of datasheet for TSOP pin configuration
Document #
SRAM122
REV B
1
Revised August 2006