P4C116/P4C116L
AC CHARACTERISTICS—WRITE CYCLE
(V
CC
= 5V ± 10%, All Temperature Ranges)
(2)
Sym.
t
WC
t
CW
t
AW
t
AS
t
WP
t
AH
t
DW
t
DH
t
WZ
t
OW
Parameter
Write Cycle Time
Chip Enable Time to End of Write
Address Valid to End of Write
Address Set-up Time
Write Pulse Width
Address Hold Time
Data Valid to End of Write
Data Hold Time
Write Enable to Output in High Z
Output Active from End of Write
–10
10
8
8
0
8
0
7
0
6
0
0
–12
12
10
10
0
10
0
8
0
7
0
–15
15
12
12
0
12
0
10
0
8
0
–20
–25
25
18
18
0
18
0
15
0
–35
35
25
25
0
20
0
20
0
Min Max Min Max Min Max Min Max Min Max Min Max
20
15
15
0
15
0
12
0
10
0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
15
0
15
ns
ns
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE CONTROLLED)
(10,11)
WE
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CE CONTROLLED)
(10)
CE
Notes:
10.
CE
and
WE
must be LOW for WRITE cycle.
11.
OE
is LOW for this WRITE cycle to show t
WZ
and t
OW
.
12. If
CE
goes HIGH simultaneously with
WE
HIGH, the output remains
in a high impedance state
13. Write Cycle Time is measured from the last valid address to the first
transitioning address.
Document #
SRAM110
REV A
Page 5 of 14
PYRAMID [ PYRAMID SEMICONDUCTOR CORPORATION ]
