P4C163/P4C163L
ULTRA HIGH SPEED 8K x 9
STATIC CMOS RAMS
FEATURES
Full CMOS, 6T Cell
High Speed (Equal Access and Cycle Times)
– 25/35ns (Commercial)
– 25/35/45ns (Military)
Low Power Operation (Commercial/Military)
Output Enable and Dual Chip Enable Control
Functions
Single 5V±10% Power Supply
Data Retention with 2.0V Supply, 10 µA Typical
Current (P4C163L Military)
Common I/O
Fully TTL Compatible Inputs and Outputs
Standard Pinout (JEDEC Approved)
– 28-Pin 300 mil DIP, SOJ
– 28-Pin 350 x 550 mil LCC
– 28-Pin CERPACK
DESCRIPTION
The P4C163 and P4C163L are 73,728-bit ultra high-speed
static RAMs organized as 8K x 9. The CMOS memories re-
quire no clocks or refreshing and have equal access and
cycle times. Inputs are fully TTL-compatible. The RAMs
operate from a single 5V±10% tolerance power supply.
With battery backup, data integrity is maintained for supply
voltages down to 2.0V. Current drain is 10 µA from a 2.0V
supply.
Access times as fast as 25 nanoseconds are available, per-
mitting greatly enhanced system operating speeds. CMOS
is used to reduce power consumption in both active and
standby modes.
The P4C163 and P4C163L are available in 28-pin 300 mil
DIP and SOJ, 28-pin 350 x 550 mil LCC, and 28-pin
CERPACK packages providing excellent board level densi-
ties.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATIONS
DIP (P5, C5), SOJ (J5)
CERPACK (F4) SIMILAR
LCC (L5)
Document #
SRAM120
REV C
1
Revised August 2006
PYRAMID [ PYRAMID SEMICONDUCTOR CORPORATION ]
