P4C187/187L
AC CHARACTERISTICS - WRITE CYCLE
(V
CC
= 5V ± 10%, All Temperature Ranges)
(2)
Symbol Parameter
t
WC
t
CW
t
AW
t
AS
t
WP
t
AH
t
DW
t
DH
t
WZ
t
OW
Write Cycle Time
Chip Enable Time to
End of Write
Address Valid to End
of Write
Address Set-up Time
Write Pulse Width
Address Hold Time
from End of Write
Data Valid to End of
Write
Data Hold Time
Write Enable to
Output in High Z
Output Active from
End of Write
-10
-12
-15
-20
-25
-35
-45
-55
-70
-85
Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max
10
8
8
0
8
0
6
0
6
0
0
12
10
10
0
10
0
7
0
7
0
15
12
12
0
12
0
10
0
8
0
20
15
15
0
15
0
13
0
12
0
25
20
20
0
20
0
15
0
15
0
35
25
25
0
25
0
20
0
17
0
45
30
30
0
30
0
25
0
20
0
55
35
35
0
35
0
30
0
25
0
70
40
40
0
40
0
35
0
30
0
85
45
45
0
45
0
40
0
35
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE CONTROLLED)
(9)
WE
Notes:
9.
CE
and
WE
must be LOW for WRITE cycle.
10. If
CE
goes HIGH simultaneously with
WE
HIGH, the output remains
in a high impedance state.
11. Write Cycle Time is measured from the last valid address to the first
transition address.
Document #
SRAM111
REV B
Page 5 of 12
PYRAMID [ PYRAMID SEMICONDUCTOR CORPORATION ]
