P4C198/198L, P4C198A/198AL
TRUTH TABLES
P4C198/L
P4C198A/L
CE WE
OE
X
H
L
Mode
Standby
Output Inhibit
READ
Output
High Z
High Z
DOUT
CE1 CE2 WE
OE
X
X
H
L
X
Mode
Standby
Standby
Output Inhibit
READ
Output
High Z
High Z
High Z
DOUT
H
L
L
L
X
H
H
L
H
X
L
L
L
X
H
L
L
L
X
X
H
H
L
X
WRITE
DIN
WRITE
DIN
AC TEST CONDITIONS
Input Pulse Levels
GND to 3.0V
Input Rise and Fall Times
Input Timing Reference Level
Output Timing Reference Level
Output Load
3ns
1.5V
1.5V
See Figures 1 and 2
Figure 2. Thevenin Equivalent
Figure 1. Output Load
* including scope and test fixture.
Note:
frequency capacitor is also required between V and ground. To avoid
signal reflections, proper termination must be uCsCed; for example, a 50Ω
test environment should be terminated into a 50Ω load with 1.73V
(Thevenin Voltage) at the comparator input, and a 116Ω resistor must
be used in series with DOUT to match 166Ω (Thevenin Resistance).
Because of the ultra-high speed of the P4C198/L and P4C198A/L, care
must be taken when testing this device; an inadequate setup can cause
a normal functioning part to be rejected as faulty. Long high-inductance
leads that cause supply bounce must be avoided by bringing the VCC and
ground planes directly up to the contactor fingers. A 0.01 µF high
Document # SRAM113 REV A
Page 8 of 13
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