Internet Data Sheet
HYS72T512341H[H/J/K]P-[3.7/5]-B
Registered DDR2 SDRAM Modules
3.3
AC Characteristics
All Speed grades faster than DDR2-400B comply with DDR2-400B timing specifications(tCK = 5ns with tRAS = 40ns).
TABLE 12
Speed Grade Definition Speed Bins for DDR2–533C and DDR2–400B
Speed Grade
DDR2–533C
DDR2–400B
Unit
Note
QAG Sort Name
CAS-RCD-RP latencies
–3.7
–5
4–4–4
3–3–3
tCK
Parameter
Symbol
Min.
Max.
Min.
Max.
—
1)2)3)4)
1)2)3)4)
1)2)3)4)
1)2)3)4)5)
1)2)3)4)
1)2)3)4)
1)2)3)4)
Clock Frequency
@ CL = 3
@ CL = 4
@ CL = 5
tCK
5
8
5
8
ns
ns
ns
ns
ns
ns
ns
tCK
3.75
3.75
45
8
5
8
tCK
8
5
8
Row Active Time
Row Cycle Time
RAS-CAS-Delay
Row Precharge Time
tRAS
tRC
tRCD
tRP
70000
—
40
55
15
15
70000
—
60
15
—
—
15
—
—
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are further guaranteed for normal
OCD drive strength (EMRS(1) A1 = 0) only.
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS/DQS, RDQS/RDQS,
input reference level is the crosspoint when in differential strobe mode
3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low.
4) The output timing reference voltage level is VTT
.
5) RAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x tREFI
t
.
Rev. 1.0, 2006-12
15
11032006-VX0M-M6IH
QIMONDA [ QIMONDA AG ]
