Internet Data Sheet
HY[B/I]18T512[40/80/16]0B2[C/F](L)
512-Mbit Double-Data-Rate-Two SDRAM
FIGURE 2
Chip Configuration for ×8 components, PG-TFBGA-60 (top view)
ꢅ
ꢈ
ꢆ
ꢃ
ꢉ
ꢂ
ꢇ
ꢊ
ꢁ
$
9''
966
9664
9''4
1&ꢄ5'46
'46
9664
9664
%
&
'
(
)
*
+
-
'4ꢂ
'0ꢄ5'46
'46
'4ꢇ
9''4
9''4
9''4
9''4
'4ꢅ
'4ꢀ
9664
9664
'4ꢃ
'4ꢆ
'4ꢈ
966'/
5$6
&$6
$ꢈ
'4ꢉ
9''/
95()
966
9''
&.
&.
&.(
%$ꢀ
$ꢅꢀꢄ$3
$ꢆ
:(
%$ꢅ
$ꢅ
2'7
1&ꢋꢌ%$ꢈ
&6
9''
$ꢀ
966
$ꢉ
$ꢂ
$ꢃ
966
.
/
$ꢇ
$ꢁ
$ꢅꢅ
1&
$ꢊ
9''
$ꢅꢈ
1&
1&ꢋꢌ$ꢅꢆ
0337ꢀꢀꢁꢀ
Notes
4. VDDL and VSSDL are power and ground for the DLL. VDDL is
connected to VDD on the device. VDD, VDDQ, VSSDL, VSS
and VSSQ are isolated on the device.
5. Ball position L8 is A13 for 512-Mbit and is Not Connected
on 256-Mbit.
,
1. RDQS / RDQS are enabled by EMRS(1) command.
2. If RDQS / RDQS is enabled, the DM function is disabled
3. When enabled, RDQS & RDQS are used as strobe
signals during reads.
Rev. 1.12, 2007-05
16
10062006-YPTZ-CDR7
QIMONDA [ QIMONDA AG ]
