Internet Data Sheet
HYB18TC256[80/16]0BF
256-Mbit Double-Data-Rate-Two SDRAM
2.2
Chip Configuration for PG-TFBGA-84
The chip configuration of a DDR2 SDRAM is listed by function in
The abbreviations used in the Ball# columns are
explained in
and
respectively.
TABLE 9
Chip Configuration of DDR SDRAM
Ball#
Name
Ball
Type
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Buffer
Type
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Address Signal 12:0,Address Signal 10/Autoprecharge
Chip Select
Bank Address Bus 1:0
Clock Enable
Row Address Strobe (RAS), Column Address Strobe (CAS), Write
Enable (WE)
Function
Clock Signals
×16
Organization
J8
K8
K2
K7
L7
K3
L8
L2
L3
M8
M3
M7
N2
N8
N3
N7
P2
P8
P3
M2
P7
R2
CK
CK
CKE
RAS
CAS
WE
CS
BA0
BA1
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
AP
A11
A12
Clock Signal CK, CK
Control Signals
×16
Organization
Address Signals
×16
Organization
Rev. 1.3, 2007-05
07182006-DD60-22E6
10
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