Internet Data Sheet
HYS[64/72]T[16/32/64]0xxHU–[2.5/../5]–A
Unbuffered DDR2 SDRAM Modules
2
Pin Configuration
The pin configuration of the Unbuffered DDR2 SDRAM DIMM is listed by function in Table 5 (240 pins). The abbreviations used
in columns Pin and Buffer Type are explained in Table 6 and Table 7 respectively. The pin numbering is depicted in Figure 1
for non-ECC modules (×64) and Figure 2 for ECC modules (×72).
TABLE 5
Pin Configuration of UDIMM
Ball No.
Name Pin
Buffer Function
Type Type
Clock Signals
185
137
220
186
138
221
52
CK0
CK1
CK2
CK0
CK1
CK2
CKE0
CKE1
NC
I
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
—
Clock Signals 2:0, Complement Clock Signals 2:0
I
I
I
I
I
I
Clock Enable Rank 1:0
Note: 2 Ranks module
171
I
NC
Not Connected
Note: 1 Rank module
Control Signals
193
76
S0#
S1#
NC
I
SSTL
SSTL
—
Chip Select Rank 1:0
Note: 2 Ranks module
I
NC
Not Connected
Note: 1 Rank module
Row Address Strobe
Column Address Strobe
Write Enable
192
RAS
CAS
WE
I
I
I
SSTL
SSTL
SSTL
74
73
Address Signals
71
BA0
BA1
BA2
I
I
I
SSTL
SSTL
SSTL
Bank Address Bus 1:0
190
54
Bank Address Bus 2
Greater than 512Mb DDR2 SDRAMS
NC
NC
—
Not Connected
Less than 1Gb DDR2 SDRAMS
Rev. 1.41, 2006-11
6
03062006-0GN5-WTPW
QIMONDA [ QIMONDA AG ]
