HY[B/E]18L256169BF-7.5
256-Mbit Mobile-RAM
Overview
1
1.1
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Overview
Features
4 banks
×
4 Mbit
×
16 organization
Fully synchronous to positive clock edge
Four internal banks for concurrent operation
Programmable CAS latency: 2, 3
Programmable burst length: 1, 2, 4, 8 or full page
Programmable wrap sequence: sequential or interleaved
Programmable drive strength
Auto refresh and self refresh modes
8192 refresh cycles / 64 ms
Auto precharge
Commercial (0°C to +70°C) and Extended (-25°C to +85°C) operating temperature range
54-ball PG-VFBGA package (11.0
×
8.0
×
1.0 mm)
RoHS Compliant Product
1)
Power Saving Features
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Low supply voltages:
V
DD
= 1.70V to 1.95V,
V
DDQ
= 1.70V to 1.95V
Optimized self refresh (
I
DD6
) and standby currents (
I
DD2
/
I
DD3
)
Programmable Partial Array Self Refresh (PASR)
Temperature Compensated Self-Refresh (TCSR), controlled by on-chip temperature sensor
Power-Down and Deep Power Down modes
Performance
- 7.5
133
CL = 3
CL = 2
Clock Cycle Time (
t
CKmin
)
CL = 3
CL = 2
Table 2
Item
Banks
Rows
Columns
Memory Addressing Scheme
Addresses
BA0, BA1
A0 - A12
A0 - A8
5.4
6.0
7.5
9.5
Unit
MHz
ns
ns
ns
ns
Table 1
Part Number Speed Code
Speed Grade
Access Time (
t
ACmax
)
1)RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and
electronic equipment as defined in the directive 2002/95/EC issued by the European Parliament and of the Council
of 27 January 2003. These substances include mercury, lead, cadmium, hexavalent chromium, polybrominated
biphenyls and polybrominated biphenyl ethers.
Data Sheet
3
Rev. 1.02, 2006-12
02032006-MP0M-7FQG
QIMONDA [ QIMONDA AG ]
