Internet Data Sheet
HYB25D512[40/16/80]0B[E/F/C/T](L)
Double-Data-Rate SDRAM
2
Pin Configuration
The pin configuration of a DDR SDRAM is listed by function in Table 4 (60 pins). The abbreviations used in the Pin#/Buffer#
column are explained in Table 5 and Table 6 respectively. The pin numbering for FBGA is depicted in Figure 1 and that of the
TSOP package in Figure 2
TABLE 4
Pin Configuration of DDR SDRAM
Ball#/Pin#
Name
Pin
Type
Buffer
Type
Function
Clock Signals
G2, 45
CK
I
I
I
SSTL
SSTL
SSTL
Clock Signal
G3, 46
CK
Complementary Clock Signal
Clock Enable
H3, 44
CKE
Control Signals
H7, 23
RAS
CAS
WE
I
I
I
I
SSTL
SSTL
SSTL
SSTL
Row Address Strobe
Column Address Strobe
Write Enable
G8, 22
G7, 21
H8, 24
CS
Chip Select
Address Signals
J8, 26
J7, 27
K7, 29
L8, 30
L7, 31
M8, 32
M2, 35
L3, 36
L2, 37
K3, 38
K2, 39
J3, 40
K8, 28
BA0
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Bank Address Bus 2:0
Address Bus 11:0
BA1
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
AP
A11
A12
J2, 41
H2, 42
Address Signal 12
Note: 256 Mbit or larger dies
Note: 128 Mbit or smaller dies
Address Signal 13
NC
NC
I
—
F9, 17
A13
SSTL
Note: 1 Gbit based dies
Note: 512 Mbit or smaller dies
NC
NC
—
Rev. 1.63, 2006-09
7
03062006-PFFJ-YJY2
QIMONDA [ QIMONDA AG ]
