Internet Data Sheet
HY[B/I]18T1G[40/80/16]0B[C/F](L/V)
1-Gbit Double-Data-Rate-Two SDRAM
2
Configuration
This chapter contains the chip configuration and addressing.
2.1
Chip Configuration for PG-TFBGA-68
The chip configuration of a DDR2 SDRAM is listed by function in Table 7. The abbreviations used in the Ball# and Buffer Type
columns are explained in Table 8 and Table 9 respectively. The ball numbering for the FBGA package is depicted in figures.
TABLE 7
Chip Configuration of DDR2 SDRAM
Ball#
Name
Ball
Type
Buffer
Type
Function
Clock Signals ×4×8 Organizations
J8
CK
I
I
I
SSTL
SSTL
SSTL
Clock Signal CK, CK
Clock Enable
K8
K2
CK
CKE
Control Signals ×4×8 Organizations
K7
L7
K3
L8
RAS
CAS
WE
I
I
I
I
SSTL
SSTL
SSTL
SSTL
Row Address Strobe (RAS), Column Address Strobe (CAS), Write
Enable (WE)
CS
Chip Select
Address Signals ×4×8 Organizations
L2
L3
L1
BA0
BA1
BA2
I
I
I
SSTL
SSTL
SSTL
Bank Address Bus 1:0
Bank Address Bus 2
Note: 1 Gbit components and higher
Rev. 1.3, 2007-07
9
03062006-ZNH8-HURV
QIMONDA [ QIMONDA AG ]
