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HYI18T1G400BC-3S 参数 Datasheet PDF下载

HYI18T1G400BC-3S图片预览
型号: HYI18T1G400BC-3S
PDF下载: 下载PDF文件 查看货源
内容描述: 1千兆位双数据速率- SDRAM双 [1-Gbit Double-Data-Rate-Two SDRAM]
分类和应用: 动态存储器
文件页数/大小: 74 页 / 4044 K
品牌: QIMONDA [ QIMONDA AG ]
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Internet Data Sheet  
HY[B/I]18T1G[40/80/16]0B[C/F](L/V)  
1-Gbit Double-Data-Rate-Two SDRAM  
2.2  
Chip Configuration for PG-TFBGA-84  
The chip configuration of a DDR2 SDRAM is listed by function in Table 10. The abbreviations used in the Ball#/Buffer Type  
columns are explained in Table 11 and Table 12 respectively.  
TABLE 10  
Chip Configuration of DDR SDRAM  
Ball#  
Name  
Ball  
Type  
Buffer  
Type  
Function  
Clock Signals ×16 Organization  
J8  
CK  
I
I
I
SSTL  
SSTL  
SSTL  
Clock Signal CK, CK  
Clock Enable  
K8  
K2  
CK  
CKE  
Control Signals ×16 Organization  
K7  
L7  
K3  
L8  
RAS  
CAS  
WE  
I
I
I
I
SSTL  
SSTL  
SSTL  
SSTL  
Row Address Strobe (RAS), Column Address Strobe (CAS), Write  
Enable (WE)  
CS  
Chip Select  
Address Signals ×16 Organization  
L2  
BA0  
BA1  
BA2  
A0  
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
Bank Address Bus 2:0  
Note: 1 Gbit components and higher  
L3  
L1  
M8  
M3  
M7  
N2  
N8  
N3  
N7  
P2  
P8  
P3  
M2  
Address Signal 12:0, Address Signal 10/Autoprecharge  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
A9  
A10  
AP  
A11  
A12  
P7  
R2  
Rev. 1.3, 2007-07  
14  
03062006-ZNH8-HURV