Internet Data Sheet
HYI25D512160C[C/E/F/T]
512-Mbit Double-Data-Rate SDRAM
2
Chip Configuration
The pin configuration of a DDR SDRAM is listed by function in Table 4 (60 pins). The abbreviations used in the Pin#/Buffer#
column are explained in Table 5 and Table 6 respectively. The pin numbering for FBGA is depicted in Figure 1 and that of the
TSOP package in Figure 2.
TABLE 4
Ball Configuration of DDR SDRAM
Ball#/Pin#
Name
Pin
Type
Buffer
Type
Function
Clock Signals
G2, 45
CK1
CK1
CKE
I
I
I
SSTL
SSTL
SSTL
Clock Signal
G3, 46
Complementary Clock Signal
Clock Enable
H3, 44
Control Signals
H7, 23
RAS
CAS
WE
I
I
I
I
SSTL
SSTL
SSTL
SSTL
Row Address Strobe
Column Address Strobe
Write Enable
G8, 22
G7, 21
H8, 24
CS
Chip Select
Address Signals
J8, 26
J7, 27
K7, 29
L8, 30
L7, 31
M8, 32
M2, 35
L3, 36
L2, 37
K3, 38
K2, 39
J3, 40
K8, 28
BA0
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Bank Address Bus 2:0
Address Bus 11:0
BA1
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
AP
A11
A12
J2, 41
H2, 42
Address Signal 12
Note: Module based on 256 Mbit or larger dies
Note: Module based on 128 Mbit or smaller dies
NC
NC
—
Rev. 1.0, 2006-11
6
11082006-S9OT-UFSN
QIMONDA [ QIMONDA AG ]
