Preliminary Internet Data Sheet
HYI25DC512[16/80]0CE
512-Mbit Double-Data-Rate SDRAM
TABLE 6
Mode Register Definition
Field
BL
Bits
[2:0]
Type
1)
W
Description
Burst Length
Number of sequential bits per DQ related to one read/write command.
Note: All other bit combinations are RESERVED.
001
B
2
010
B
4
011
B
8
BT
3
Burst Type
See
for internal address sequence of low order address bits.
0 Sequential
1 Interleaved
CAS Latency
Number of full clocks from read command to first data valid window.
Note: All other bit combinations are RESERVED.
010
B
011
B
110
B
101
B
Note:
MODE
[12:7]
2
3
2.5
1.5
CL = 1.5 for DDR200 components only
CL
[6:4]
Operating Mode
Note: All other bit combinations are RESERVED.
000000 Normal Operation without DLL Reset
000010 Normal Operation with DLL Reset
1) W = write only register bit
Rev. 0.7, 2006-12
11292006-TAIE-H645
10
QIMONDA [ QIMONDA AG ]
