Internet Data Sheet
HY[B/I]39SC128[800/160]FE
128-MBit Synchronous DRAM
2
2.1
Pin Configuration
Pin Configuration
This chapter contains the pin configuration for the
×8, ×16
organization of the SDRAM.
Listed below are the pin configurations sections for the various signals of the SDRAM.
TABLE 3
Pin Configuration of the SDRAM
Ball No.
Name
Pin
Type
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Buffer
Type
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
Address Signal 9:0, Address Signal 10/Auto precharge
Chip Select
Bank Address Signals 1:0
Function
Clock Signals
×8/×16
Organization
38
37
18
17
16
19
20
21
23
24
25
26
29
30
31
32
33
34
22
35
CLK
CKE
RAS
CAS
WE
CS
BA0
BA1
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
Clock Signal CK
Clock Enable
Row Address Strobe (RAS), Column Address Strobe (CAS), Write Enable (WE)
Control Signals
×8/×16
Organization
Address Signals
×8/×16
Organization
Rev. 1.1, 2007-02
09072006-N4GC-EREN
5
QIMONDA [ QIMONDA AG ]
