Internet Data Sheet
HYS[64/72]D[32/64/128]xxx[G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
TABLE 4
Abbreviations for Pin Type
Abbreviation
I
O
I/O
AI
PWR
GND
NC
Description
Standard input-only pin. Digital levels.
Output. Digital levels.
I/O is a bidirectional input/output signal.
Input. Analog levels.
Power
Ground
Not Connected
TABLE 5
Abbreviations for Buffer Type
Abbreviation
SSTL
LV-CMOS
CMOS
OD
Description
Serial Stub Terminated Logic (SSTL2)
Low Voltage CMOS
CMOS Levels
Open Drain. The corresponding pin has 2 operational states, active low and tristate, and
allows multiple devices to share as a wire-OR.
TABLE 6
Address Format
Density
256 MB
512 MB
512 MB
1 GB
1 GB
Organization
32M
×64
64M
×64
64M
×72
128M
×64
128M
×72
Memory
Ranks
1
1
1
2
2
SDRAMs
32M
×16
64M
×8
64M
×8
64M
×8
64M
×8
# of
SDRAMs
4
8
8
16
18
# of row/bank/
columns bits
13/2/9
13/2/11
13/2/11
13/2/12
13/2/12
Refresh
8K
8K
8K
8K
8K
Period
64 ms
64 ms
64 ms
64 ms
64 ms
Interval
7.8 ms
7.8 ms
7.8 ms
7.8 ms
7.8 ms
Rev. 1.22, 2007-01
03292006-CXBY-V2JX
12
QIMONDA [ QIMONDA AG ]
