Internet Data Sheet
HYS64T[32/64/128]xxxEDL–[25F/…/3.7](–)B2
Small Outlined DDR2 SDRAM Modules
Pin No.
109
Address Signals
107
106
85
Name
WE
BA0
BA1
BA2
NC
Pin
Type
I
I
I
I
NC
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
NC
I
NC
Buffer
Type
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
—
SSTL
—
Function
Write Enable
Bank Address Bus 2:0
Selects which DDR2 SDRAM internal bank of four or eight
is activated.
Bank Address Bus 2
Greater than 512Mb DDR2 SDRAMS
Less than 1Gb DDR2 SDRAMS
Address Bus 12:0
During a Bank Activate command cycle, defines the row
address when sampled at the cross-point of the rising edge
of CK and falling edge of CK. During a Read or Write
command cycle, defines the column address when sampled
at the cross point of the rising edge of CK and falling edge
of CK. In addition to the column address, AP is used to
invoke autoprecharge operation at the end of the burst read
or write cycle. If AP is HIGH, autoprecharge is selected and
BA0-BAn defines the bank to be precharged. If AP is LOW,
autoprecharge is disabled. During a Precharge command
cycle, AP is used in conjunction with BA0-BAn to control
which bank(s) to precharge. If AP is HIGH, all banks will be
precharged regardless of the state of BA0-BAn inputs. If AP
is LOW, then BA0-BAn are used to define which bank to
precharge.
Address Signal 12
Note: Module based on 256 Mbit or larger dies
Address Signal 13
Note: 1 Gbit based module
Not Connected
Note: Module based on 512 Mbit or smaller dies
Address Signal 14
Note: 2 Gbit based module
Not Connected
Note: Module based on 1 Gbit or smaller dies
Data Bus 63:0
Note: Data Input / Output pins
102
101
100
99
98
97
94
92
93
91
105
90
89
116
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
AP
A11
A12
A13
NC
86
A14
NC
Data Signals
5
7
17
19
4
6
14
16
23
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Rev. 1.13, 2007-10
08212006-PKYN-2H1B
7
QIMONDA [ QIMONDA AG ]
