Internet Data Sheet
HYS[64/72]T[32/64/128][0/9]xxEU-[25F/2.5/3/3S/3.7]-B2
Unbuffered DDR2 SDRAM Module
1.2
Description
The memory array is designed with 512-Mbit Double-Data-
Rate-Two (DDR2) Synchronous DRAMs. Decoupling
capacitors are mounted on the PCB board. The DIMMs
feature serial presence detect based on a serial E
2
PROM
device using the 2-pin I
2
C protocol. The first 128 bytes are
programmed with configuration data and are write protected;
the second 128 bytes are available to the customer.
The
Qimonda
HYS[64/72]T[32/64/128][0/9]xxEU-
[25F/2.5/3/3S/3.7]-B2 module family are unbuffered DIMM
modules “UDIMMs” with 30,0 mm height based on DDR2
technology. DIMMs are available as non-ECC modules in
32M
×
64 (256 MB),
64M
×
64 (512 MB)
and
128M
×
64 (1 GB) and ECC modules in 64M
×
72 (512 MB),
128M
×
72 (1 GB) organization and density, intended for
mounting into 240-pin connector sockets.
TABLE 2
Ordering Information for RoHS Compliant Products
Product Type
1)
PC2–6400
HYS64T32000EU–25F–B2
HYS64T32900EU–25F–B2
HYS64T64000EU–25F–B2
HYS64T64900EU–25F–B2
HYS72T64000EU–25F–B2
HYS72T64900EU–25F–B2
HYS64T128020EU–25F–B2
HYS64T128920EU–25F–B2
HYS72T128020EU–25F–B2
HYS72T128920EU–25F–B2
PC2–6400
HYS64T32000EU–2.5–B2
HYS64T32900EU–2.5–B2
HYS64T64000EU–2.5–B2
HYS64T64900EU–2.5–B2
HYS72T64000EU-2.5–B2
HYS72T64900EU-2.5–B2
HYS64T128020EU–2.5–B2
HYS64T128920EU–2.5–B2
HYS72T128020EU–2.5–B2
HYS72T128920EU–2.5–B2
PC2–5300
HYS64T32000EU–3–B2
HYS64T32900EU–3–B2
HYS64T64000EU–3–B2
HYS64T64900EU–3–B2
HYS72T64000EU–3–B2
HYS72T64900EU–3–B2
256MB 1R×16 PC2-5300U–444–12–C1
512MB 1R×8 PC2–5300U–444–12–D0
512MB 1R×8 PC2–5300E–444–12–F0
1 Rank, Non-ECC
1 Rank, Non-ECC
1 Rank, ECC
512 Mbit (×16)
512 Mbit (×8)
512 Mbit (×8)
256MB 1R×16 PC2–6400U–666–12–C1
512 MB 1R×8 PC2–6400U–666–12–D0
512MB 1R×8 PC2–6400E–666–12–F0
1GB 2R×8 PC2–6400U–666–12–E0
1GB 2R×8 PC2–6400E–666–12–G0
1 Rank, Non-ECC
1 Rank, Non-ECC
1 Rank, ECC
2 Ranks, Non-ECC
2 Ranks, ECC
512 Mbit (×16)
512 Mbit (×8)
512 Mbit (×8)
512 Mbit (×8)
512 Mbit (×8)
256MB 1R×16 PC2–6400U–555–12–C1
512 MB 1R×8 PC2–6400U–555–12–D0
512MB 1R×8 PC2–6400E–555–12–F0
1GB 2R×8 PC2–6400U–555–12–E0
1GB 2R×8 PC2–6400E–555–12–G0
1 Rank, Non-ECC
1 Rank, Non-ECC
1 Rank, ECC
2 Ranks, Non-ECC
2 Ranks, ECC
512 Mbit (×16)
512 Mbit (×8)
512 Mbit (×8)
512 Mbit (×8)
512 Mbit (×8)
Compliance Code
2)
Description
SDRAM
Technology
Rev. 1.0, 2006-10
10202006-L0SM-FEYT
4
QIMONDA [ QIMONDA AG ]
