2 Device Operation
2.1 Start-up Time
After a reset or power-up event, the device requires 300ms to
initialize, calibrate, and start operating normally. Keys will work
properly once all keys have been calibrated after reset.
2.5 DETECT Pin
DETECT represents the functional logical-OR of all eight
keys. DETECT can be used to wake up a battery-operated
product upon human touch.
DETECT is also required to indicate to a host when the binary
coded output pins (in that mode) are showing an active key.
While DETECT is active, the binary coded outputs should be
read at least twice along with DETECT to make sure that the
code was not transitioning between states, to prevent a false
reading.
The output polarity and drive of DETECT are governed
according to Table 1.4.
2.2 Option Resistors
The option resistors are read on power-up only; it is not
possible to change the operating mode of the device once it
has powered up. There are two primary option mode
configurations: Full, and simplified.
Full options mode:
Eight 1M option resistors are required
as shown in Figure 1.1. All eight resistors are mandatory.
Simplified mode:
A 1M resistor should be connected from
SNS6K to SNS7. In simplified mode, only one additional 1M
option resistor is required for the AKS feature (Figure 1.2).
Note that the presence and connection of option resistors will
affect the required values of Cs; this effect will be especially
noticeable if the Cs values are under 22nF. Cs values should
be adjusted for optimal sensitivity after the option resistors are
connected.
2.6 SYNC/LP Pin
When full options are in use, the SYNC/LP pin function is
selected according to the SL_0 and SL_1 resistor connections
as given in Table 1.5. When the QT1081 is in sync mode the
pin acts as a SYNC input; when the QT1081 is in LP mode the
pin acts as an LP input.
When simplified options are in use, the QT1081 is always in
LP mode and the SYNC/LP pin acts as an LP input.
Sync mode:
Sync mode allows the designer to synchronize
acquire bursts to an external signal source, such as mains
frequency (50/60 Hz) to suppress interference. It can also be
used to synchronize two QT parts which operate near each
other, so that only one part generates acquire bursts at a time
and hence they do not cross-interfere.
The SYNC input of the QT1081 is positive edge triggered.
Following each rising edge the QT1081 will generate a pair of
acquire bursts in A-B sequence; this operation is shown in
Figure 2.1.
2.3 One-per-key Output Mode
One-per-key output mode is selected via option resistors, as
shown in Table 1.4.
In this mode, there is one output for each key; each is active
when a touch is confirmed on the corresponding electrode.
Unused OUT pins should be left open.
If AKS is off, it is possible for all OUT pins to be active at the
same time.
Circuit of Figure 1.1:
OUT polarity and drive are governed by
the resistor connections to Vdd or Vss according to Table 1.4.
The drive can be either push-pull or open-drain, active low or
high.
Circuit of Figure 1.2:
In this simplified circuit, the OUT pins
are active high, push-pull only.
Figure 2.1 Acquire Bursts in A-B Sequence
SYNC
Burst A
Burst B
If the SYNC input does not change level for ~150ms, the
QT1081 will free-run, generating a continuous stream of
acquire bursts A-B-A-B-A-... . While the QT1081 is in free-run
operation, a rising edge on the SYNC input will return the
QT1081 to synchronised operation.
Note that the SYNC input must remain at one level (high or
low) for >150µs to guarantee that the QT1081 will recognise
that level.
Low Power LP Mode:
LP mode allows the device to be
switched between full speed operation (20ms typical response
time and normal power consumption), and Low Power
operation (low average power consumption but an increased
maximum response time) according to the needs of the
application. There are three maximum response time settings
for low power operation: 100ms, 180ms, and 340ms nominal;
the response time setting is determined by option resistors
SL_1 and SL_0; see Table 1.5. Slower response times result
in a lower average power drain.
2.4 Binary Coded Output Mode
This mode is useful to reduce the number of connections to a
host controller, at the expense of only being able to report one
active key at a time. Note that in global AKS mode (Section
2.7), only one key can report active at a time anyway. Binary
coded mode is selected via option resistors, as shown in
Table 1.4.
In this mode, a key detection is registered as a binary code on
pins OUT_2, OUT_1 and OUT_0, with possible values from
000 to 111. In practice, four lines are required to read the
code, unless key 0 is not implemented; the output code 000
can mean either ‘nothing detecting’ or ‘key 0 is detecting’. The
fourth required line (if all eight keys are implemented) is the
DETECT signal, which is active-high when any key is active.
The first key touched always wins and shows its output. Keys
that come afterwards are hidden until the currently reported
key has stopped detecting, in which case the code will change
to a latent key.
Circuit of Figure 1.1:
OUT polarity and drive can only be
push-pull and active high.
Circuit of Figure 1.2:
Binary coded not available.
lQ
8
QT1081_1R0.04_0307
QUANTUM [ QUANTUM RESEARCH GROUP ]
