prevent cross interference, unless they are
synchronized.
6.
7.
Keep the electrode (and its wiring) away from other
traces carrying AC or switched signals.
If there are LEDs or LED wiring near the electrode or its
wiring (ie for backlighting of the key), bypass the LED
wiring to ground on both the anode and cathode.
Use a voltage regulator just for the QT510 to eliminate
noise coupling from other switching sources via Vdd.
Make sure the regulator’s transient load stability provides
for a stable voltage just before each burst commences.
If Mains noise (50/60 Hz noise) is present, use the Sync
feature to suppress it (see Section 1.1).
3 Serial Communications
The serial interface is a SPI slave-only mode type which is
compatible with multi-drop operation, ie the MISO pin will float
after a shift operation to allow other SPI devices (master or
slave) to talk over the same bus. There should be one
dedicated /SS line for each QT510 from the host controller.
A DRDY (‘data ready’) line is used to indicate to the host
controller when it is possible to talk to the QT510.
8.
3.1 Power-up Timing Delay
Immediately after power-up, DRDY floats for approximately
20ms, then goes low. The device requires ~520ms thereafter
before DRDY goes high again, indicating that the device has
calibrated and is able to communicate.
9.
For further tips on construction, PCB design, and EMC issues
browse the application notes and faq at
www.qprox.com
3.2 SPI Timing
The SPI interface is a five-wire slave-only type; timings are
found in Figure 3-1. The phase clocking is as follows:
Clock idle:
Data out changes on:
Input data read on:
Slave Select /SS:
Data Ready DRDY:
Bit length & order:
Clock rate:
High
Falling edge of CLK from host
Rising edge of CLK from host
Negative level frame from host
Low from QT inhibits host
8 bits, MSB shifts first
5kHz min, 40kHz max
The host can shift data to and from the QT on the same cycle
(with overlapping commands). Due to the nature of SPI, the
Figure 3-1 SPI Timing Diagram
~31ms
Acquire Burst
<1ms, ~920us typ
Sleep Mode
awake
low-power sleep; 1s max
400us typ
3-state if left to float
DRDY from QT
>13uS, <100uS
>12us, <100us
>12us, <100us
<30uS
/SS from host
>35uS
Data sampled on rising edge
CLK from Host
Data shifts out on falling edge
Host Data Output
(Slave Input - MOSI)
data hold >=12us
after last clock
0
?
<9us delay
edge to data
7
6
5
4
3
2
1
command byte
response byte
? 7
6
5
4
3
2
1
0
3-state
output floats
before DRDY
goes low
QT Data Output
(Slave Out - MISO)
3-state
output driven
<11us after /SS
goes low
lQ
6
QT510 R6.04/0505
QUANTUM [ QUANTUM RESEARCH GROUP ]
