© Quantum Research Group Ltd.
External fields can cause interference leading to false
Cs when the drive signal is low, so ^S should be set to ‘0’.
Figure 3-2 requires that ^S be set to ‘1’.
detections or sensitivity shifts. Most fields come from AC
power sources. RFI noise sources are heavily suppressed by
the low impedance nature of the QT circuitry itself.
This feature allows for operation with the two basic circuit
topologies which require different Cs reset control polarities.
External noise becomes a problem if the noise is uncorrelated
with signal sampling; uncorrelated noise can cause aliasing
effects in the key signals. To suppress this problem the
devices feature a noise sync input which allows bursts to
synchronize to the noise source. This same input can also be
used to wake the part from a low-power Sleep state.
3.20 Oscilloscope Sync
See also Command ^R, page 29
‘MS’ pin 37 can output a positive pulse oscilloscope sync that
brackets the burst of a selected key. This feature is controlled
by the ^R command. More than one burst can output a sync
pulse, for example if the scope of the command when set is
a row or column, or is all keys. The ^R command is volatile
and does not survive reset or power down.
The device’s bursts can be synchronized to an external
source of repetitive electrical signal, such as 50Hz or 60Hz,
or possibly a video display vertical sync line, using the
Sleep_wake / Noise sync line. The noise sync operating
mode is set by command ^W. This feature allows dominant
external noise signals to be heavily suppressed, since the
system and the noise become synchronized and no longer
beat or alias with respect to each other. The sync occurs
only at the burst for key 0 (X0Y0); the device waits for the
sync signal for up to 100ms after the end of a preceding full
matrix scan (after key #63), then when a negative sync edge
is received, the matrix is scanned in its entirety again.
This feature is invaluable for diagnostics; without it, observing
signals clearly on an oscilloscope for a particular burst is
nearly impossible.
This pin is also used as a SPI mode select pin. In order to
prevent a shorted output when the oscilloscope sync is
enabled, the MS pin should only be connected to ground or
Vdd via a m10K resistor.
This function is supported in QmBtn PC software via a
checkbox.
The sync signal drive should be a buffered logic signal, or
perhaps a diode-clamped signal, but never a raw AC signal
from the mains.
3.21 Power Supply and PCB Layout
Since Noise sync is highly effective yet simple and
Vdd should be 5.0 volts +/- 5%. This can be provided by a
common 78L05 3-terminal regulator. LDO type regulators are
usually fine but can suffer from poor transient load response
which may cause erratic signal behavior.
inexpensive to implement, it is strongly advised to take
advantage of it anywhere there is a possibility of encountering
electric fields. Quantum’s QmBtn software can show signal
noise caused by nearby AC electric fields and will hence
assist in determining the need to make use of this feature.
If the power supply is shared with another electronic system,
care should be taken to assure that the supply is free of
digital spikes, sags, and surges which can adversely affect
the circuit. The devices can track slow changes in Vcc
depending on the settings of drift compensation, but signals
can be adversely affected by rapid voltage steps and impulse
noise on the supply rail.
If the sync feature is enabled but no sync signal exists, the
sensor will continue to operate but with a delay of 100ms
from the end of one scan to the start of the next, and hence
will have a slow response time.
3.18 LED / Alert Output
0.1µF bypass caps from power to ground should be used
near every supply pin of every active component in the circuit.
Pin 40 is designed to drive a low-current LED, 5mA
maximum, active-low. The LED will glow brightly (i.e. pin 40
will be solid low) during calibration of one or more keys, for
example at startup. When a key is detected, pin 40 will be low
for the duration of each burst for which a key is sensed, i.e.
with a very low duty cycle. Each additional key being detected
will also create a low pulse for that key’s burst. During all
other times, the LED pin will be inactive (high).
Vee is a negative supply used by the circuit of Figure 3-1; it
can range from -3V to -5V. It does not need to be regulated
but should be well filtered and free from external fluctuations.
Figure 3-1 shows a simple, inexpensive charge-pump which
is driven from resonator pin XTO to generate Vee.
Current requirements of the circuit are approximately
20mA / Vdd, 4mA / Vee when running.
This pin can be used to alert the host that there is key activity,
in order to limit the amount of communication between the
device and the host. The LED / Alert line should ideally be
connected to an interrupt pin on the host that can detect a
negative edge, following which the host can proceed to poll
the device for key activations.
PCB layout: The PCB layout should incorporate a ground
plane under the entire circuit; this is possible even with
2-layer boards. The ground plane should be broken up as
little as possible. Internal nodes of the circuit can be quite
sensitive to external noise and the circuit should be kept
away from stray magnetic and electric fields, for example
those emanating from mains power components such as
transformers and power capacitors. If proximity to such
components is unavoidable, an electrostatic shield should be
considered. The Sync feature (Section 3.17) can also be
invaluable in reducing these types of noise sources.
This pin also pulls low if there is a key error of any kind.
Note that in sleep mode if the LED was on just prior to sleep,
it will remain on during sleep.
3.19 CSR Drive Polarity
See also Command ^S, page 29
Sample layout artwork is available from Quantum on request.
The polarity of the Cs integrator capacitor reset drive can be
set for active high or active low operation using command ^S.
In the reference circuit show in Figure 3-1, the JFET will reset
lQ
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