© Quantum Research Group Ltd.
force an update of eeprom from Flash memory if not
legitimate.
operation. To accomplish this, the PLD always clamps all Y
lines to ground except during the rise of X for the key being
scanned.
Charge integrator.
The first opamp is configured as an
integrator with a reset switch; capacitor Cs (C14 in Figure
3-1, and C7 in Figure 3-2) performs the charge integration
function. Capacitor Ca (C11 in Figure 3-1 only) acts to absorb
charge momentarily before the Figure 3-1 opamp can react to
absorb the charge across Cs; the value of Ca is not critical. A
P-channel jfet resets Cs between bursts (n-channel mosfet in
the case of Figure 3-2). The output of the opamp of Figure
3-1 swings negative, and as a consequence a negative power
supply is required for that circuit; the circuit of Figure 3-2 is
unipolar and requires only a positive supply.
Charge cancellation.
Two Cz capacitors are used to cancel
charge across Cs in stepwise fashion in order to increase
signal range. These capacitors can switch during the course
of a burst to reduce the final output of the amplifier chain,
preventing early signal saturation due to large keys (high Cx)
and/or long burst lengths. The Cz's are normally driven to
+5V when not in use; switching them to ground causes a step
subtraction of charge from the integrator.
Signal amplification; offset.
At the end of the burst, the
charge integrator result is amplified, and an offset from an
R2R ladder DAC driven off the X drive lines is applied. This
offset repositions the final analog signal as close as possible
to the center of the ADC span, or at about 2.5V. The amount
of offset applied is determined during the calibration process.
Burst / R2R timing.
Figure 3-3 relates to a particular key
being addressed by an X row line and gate control lines YSn.
At the end of the burst, the X pins drive the R2R ladder
network to generate a correction offset to the amplifier chain.
The amplifier must stabilize to within �½ LSB (10mV) 8µs after
the application of the R2R value so that the signal can be
accurately sampled by the QT60xx5 on pin Ain.
Signal gain.
Gain is directly controlled by burst length,
amplifier gain, and the value of Cs. Burst length can be
adjusted on a key by key basis whereas Av and Cs are fixed
for all keys. See Section 3.6. The detection threshold setting
also factors directly into key sensitivity.
3 Circuit Operation
Two reference circuits are shown in Figures 3-1 and 3-2.
Figure 3-1 shows a circuit having slightly greater precision
and sensitivity than that of Figure 3-2, however both will
perform well in most situations. Note that the Figure 3-2
circuit must have the Cs clamp control (command ^S) polarity
set to 0x01 to operate properly.
3.1 Part Differences
QT60xx5 parts use identical circuits and operate in identical
manner in all respects, except that only the QT60645 can
acquire 64 keys.
The QT60325 and QT60485 only acquire 32 and 48 keys
respectively, but both still use an 8x8 matrix; any 32 or 48
keys in the matrix can be used. Unused keys must be
disabled by setting their burst length to zero (command ^F).
These devices have their upper keys disabled (keys 32 and
48 and up respectively). Upper keys can be enabled by first
disabling undesired lower keys so that the maximum number
of keys is never exceeded during the setup process.
3.2 Matrix Scan Sequence
The circuit operates by scanning each key sequentially, key
by key. Key scanning begins with location X=0 / Y=0. X axis
keys are known as
rows
while Y axis keys are referred to as
columns.
Keys are scanned sequentially by row, for example
the sequence Y0X0 Y0X1 .... Y0X3, Y1X0 Y1X1... etc.
Each key is sampled from 1 to 64 times in a burst whose
length is determined by command ^F. A burst is completed
entirely before the next key is sampled; at the end of each
burst the resulting analog signal is converted to digital by the
part’s ADC. The burst length directly impacts key gain; each
key can have a unique burst length in order to allow tailoring
of key sensitivity on a key by key basis.
3.3 Signal Path
Refer to Figures 1-4, 3-1, 3-2, and 3-3. Further descriptions
can be found in Section 1.20.
Charge gate.
Only one X row is pulsed during a burst.
Charge is coupled across a key's Cx capacitance from the X
row to all Y columns. A particular key is chosen by gating the
charge from a single Y column into a charge integrator. The
gate is an 8:1 analog mux whose path is selected by lines
YS0, YS1, and YS2; the gate is enabled by a pulse from the
PLD. The charge integrator is described below.
Dwell time.
The gate must be switched closed just prior to
the rising edge of X and must be reopened just after X has
finished rising, in order to capture the charge driven across
key capacitance Cx. The delay time from the rise of X to the
opening of the gate is known as the Y-sample
dwell time.
Dwell time duration has a dramatic effect on the suppression
of signals due to moisture films as described in Section 3.13.
Dwell time is fixed in these devices to 167ns but this can be
shortened using an external circuit (Section 3.9).
Charge neutralization.
When X falls again, the charge
across Cx must be neutralized. Without neutralization, Cx
charge would be sampled one time only and not again during
3.4 'X' Electrode Drives
The 'X' lines are directly connected to the matrix without
buffering. The positive edges of these signals are used to
create the transient field flows used to scan the keys. Only
one X line is actively driving the matrix for scanning purposes
at a time, and it will pulse for a ‘burst length’ for each key as
determined by the 'Burst Length' Setups parameter (see
command ^F, page 25 and Section 3.6).
3.4.1 RFI F
ROM
X L
INES
X drive lines will radiate a small amount of RFI. This can be
attenuated if required by using series resistor in-line with
each X trace; the resistor should be placed near to the
QT60xx5. Typical values can range from 47 to 470 ohms.
Excessive amounts of R will cause a counterproductive drop
in signal strength. RC networks can also be used as shown in
Figure 4-4.
Inserted resistors in the X lines also have the positive effect
of limiting ESD transient currents (Section 3.22).
lQ
9
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QT60xx5 / R1.05
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