FM24C64
Address
By Master Start
DEVICE ADDRESS
S
By FM24C64
Acknowledge
Data
1 A
DATA BYTE
No Acknowledge
Stop
1 P
Figure 7. Current Address Read
Address
By Master Start
DEVICE ADDRESS
S
By FM24C64
Acknowledge
1 A
Acknowledge
DATA BYTE
A
DATA BYTE
A
No Acknowledge
Stop
DATA BYTE
1 P
Data
Figure 8. Sequential Read
Address
By Master
Start
DEVICE ADDRESS
S
By FM24C64
Acknowledge
Data
ADDRESS MSB
0 A X X X
A
ADDRESS LSB
Start
DEVICE ADDRESS
A S
1 A
Acknowledge
DATA BYTE
A
No Acknowledge
Stop
DATA BYTE
1 P
Figure 9. Selective (Random) Read
Endurance
Internally, a FRAM operates with a read and restore
mechanism. Therefore, endurance cycles are applied
for each read or write cycle. The FRAM architecture
is based on an array of rows which are subdivided
into segments. Rows (defined by A12-A5) are
subdivided into 4 segments (A4-A3). Each access
causes an endurance cycle for a row segment. In the
FM24C64, there are 8 bytes (defined by A2-A0) per
segment. Endurance can be optimized by ensuring
frequently accessed data is located in different
segments. Regardless, FRAM read and write
endurance is effectively unlimited at the 1MHz two-
wire speed. Even at 3000 accesses per second to the
same segment, 10 years time will elapse before 1
trillion endurance cycles occur.
Rev. 3.0
Mar. 2005
7 of 12
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
