FM24CL64
Diagram Notes
All start and stop timing parameters apply to both read and write cycles. Clock specifications are identical for read
and write cycles. Write timing parameters apply to slave address, word address, and write data bits. Functional
relationships are illustrated in the relevant datasheet sections. These diagrams illustrate the timing parameters only.
Read Bus Timing
t
R
`
t
F
t
HIGH
t
LOW
t
SP
t
SP
SCL
t
SU:SDA
t
BUF
1/fSCL
t
HD:DAT
t
SU:DAT
t
DH
SDA
Start
Stop Start
t
AA
Acknowledge
Write Bus Timing
t
HD:DAT
SCL
t
SU:STO
t
HD:STA
t
SU:DAT
t
AA
SDA
Start
Stop Start
Acknowledge
Data Retention
(V
DD
= 2.7V to 3.65V, 85°C)
Parameter
Data Retention
Min
45
Units
Years
Notes
Rev. 3.1
Mar. 2005
Page 10 of 13
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