FM24C16C - 16Kb 5V I2C F-RAM
Counter
Address
Latch
256 x 64
FRAM Array
8
SDA
`
Serial to Parallel
Converter
Data Latch
SCL
WP
Control Logic
Figure 1. Block Diagram
Pin Description
Pin Name
SDA
Type
I/O
Pin Description
Serial Data Address: This is a bi-directional data pin for the two-wire interface. It
employs an open-drain output and is intended to be wire-OR‟d with other devices on the
two-wire bus. The input buffer incorporates a Schmitt trigger for noise immunity and the
output driver includes slope control for falling edges. A pull-up resistor is required.
Serial Clock: The serial clock input for the two-wire interface. Data is clocked-out on
the falling edge and clocked-in on the rising edge.
Write Protect: When WP is high, the entire array is write-protected. When WP is low,
all addresses may be written. This pin is internally pulled down.
Supply Voltage (5V)
Ground
No connect
SCL
WP
VDD
VSS
NC
Input
Input
Supply
Supply
-
Rev. 1.1
May 2011
Page 2 of 12
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
