FM24V02 - 256Kb I2C FRAM
issues a start condition. This simultaneously aborts
the write operation and allows the read command to
be issued with the slave address LSB set to a ‘1’. The
operation is now a current address read.
By Master
Start
Address
No
Acknowledge
Stop
S
By FM24V02
Slave Address
1 A
Data Byte
1
P
Acknowledge
Data
Figure 7. Current Address Read
By Master
Start
Address
Acknowledge
No
Acknowledge
Stop
S
By FM24V02
Slave Address
1 A
Data Byte
A
Data Byte
1 P
Acknowledge
Data
Figure 8. Sequential Read
Start
By Master
S
Slave Address
0 A
Address
Start
Address
No
Acknowledge
Stop
Address MSB
A
Address LSB
A
S
Slave Address
1 A
Data Byte
1 P
By FM24V02
Acknowledge
Data
Figure 9. Selective (Random) Read
Start
By Master
S
HS-mode command
Start &
Enter HS-mode Address
No
Acknowledge
Stop &
Exit HS-mode
Data Byte
1
P
0
0
0
0
1
X
X
X
1
S
Slave Address 1 A
By FM24V02
No
Acknowledge
Acknowledge
Data
Figure 10. HS-mode Current Address Read
Start
By Master
S
HS-mode command
Start &
Enter HS-mode
Address & Data
Stop &
Exit HS-mode
0
0
0
0
1
X
X
X
1
S
Slave Address 0 A
Address MSB
A
Address LSB
A
Data Byte
A P
By FM24V02
No
Acknowledge
Acknowledge
Figure 11. HS-mode Byte Write
Rev. 2.0
May 2010
Page 7 of 16
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
