FM28V020 - 32Kx8 FRAM
chip enable must remain inactive for at least the
minimum precharge time t
PC
.
Precharge is also activated by changing the upper
addess A(14:3). The current row is first closed prior
to accessing the new row. The device automatically
detects an upper order address change which starts a
precharge operation, the new address is latched, and
the new read data is valid within the t
AA
address
access time. Refer to the
Read Cycle Timing 1
diagram on page 9. Likewise a similar sequence
occurs for write cycles. Refer to the
Write Cycle
Timing 3
diagram on page 11. The rate at which
random addresses can be issued is t
RC
and t
WC
,
respectively.
Endurance
The FM28V020 is capable of being accessed at least
10
14
times – reads or writes. An F-RAM memory
operates with a read and restore mechanism.
Therefore, an endurance cycle is applied on a row
basis. The F-RAM architecture is based on an array
of rows and columns. Rows are defined by A14-A3
and column addresses by A2-A0. The array is
organized as 4K rows of 8-bytes each. The entire row
is internally accessed once whether a single byte or
all eight bytes are read or written. Each byte in the
row is counted only once in an endurance calculation.
The user may choose to write CPU instructions and
run them from a certain address space. The table
below shows endurance calculations for 256-byte
repeating loop, which includes a starting address, 7
page mode accesses, and a CE precharge. The
number of bus clocks needed to complete an 8-byte
transaction is 8+1 at lower bus speeds, but 9+2 at
33MHz due to initial read latency and an extra clock
to satisfy the device’s precharge timing constraint t
PC
.
The entire loop causes each byte to experience only
one endurance cycle.
F-RAM read and write
endurance is virtually unlimited even at 33MHz
system bus clock rate.
Table 1. Time to Reach 100 Trillion Cycles for Repeating 256-byte Loop
Bus Freq Bus Cycle
256-byte
Endurance
Endurance
Years to
(MHz)
Time (ns) Transaction Cycles/sec.
Cycles/year
Reach 10
14
Cycles
Time (µs)
µ
12
30
10.56
33
94,690
2.98 x 10
33.5
12
40
12.8
40.6
25
78,125
2.46 x 10
12
10
100
28.8
34,720
1.09 x 10
91.7
11
5
200
57.6
17,360
5.47 x 10
182.8
Rev. 1.1
Sept. 2009
Page 5 of 14
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
