FM31278/276/274/272 - 5V I2C Companion
Overview
The FM3127x family combines a serial nonvolatile
RAM with a real-time clock (RTC) and a processor
companion. The companion is a highly integrated
peripheral including a processor supervisor, a
comparator used for early power-fail warning,
nonvolatile event counters, and a 64-bit serial
number.
The
FM3127x
integrates
these
complementary but distinct functions that share a
common interface in a single package. Although
monolithic, the product is organized as two logical
devices,
the
F-RAM
memory
and
the
RTC/companion. From the system perspective they
appear to be two separate devices with unique IDs on
the serial bus.
The memory is organized as a stand-alone 2-wire
nonvolatile memory with a standard device ID value.
The real-time clock and supervisor functions are
accessed with a separate 2-wire device ID. This
allows clock/calendar data to be read while
maintaining the most recently used memory address.
The clock and supervisor functions are controlled by
25 special function registers. The RTC and event
counter circuits are maintained by the power source
on the VBAK pin, allowing them to operate from
battery or backup capacitor power when V
DD
drops
below an internally set threshold. Each functional
block is described below.
protected addresses. The special function registers
containing these bits are described in detail below.
Write protect addresses
None
Bottom 1/4
Bottom 1/2
Full array
WP1
0
0
1
1
WP0
0
1
0
1
Processor Companion
In addition to nonvolatile RAM, the FM3127x family
incorporates a highly integrated processor
companion. It includes a low voltage reset, a
programmable watchdog timer, battery-backed event
counters, a comparator for early power-fail detection
or other purposes, and a 64-bit serial number.
Processor Supervisor
Supervisors provide a host processor two basic
functions: detection of power supply fault conditions
and a watchdog timer to escape a software lockup
condition. All FM3127x devices have a reset pin
(/RST) to drive the processor reset input during
power faults (and power-up) and software lockups. It
is an open drain output with a weak internal pull-up
to V
DD
. This allows other reset sources to be wire-
OR’d to the /RST pin. When V
DD
is above the
programmed trip point, /RST output is pulled weakly
to V
DD
. If V
DD
drops below the reset trip point
voltage level (V
TP
) the /RST pin will be driven low. It
will remain low until V
DD
falls too low for circuit
operation which is the V
RST
level. When V
DD
rises
again above V
TP
, /RST will continue to drive low for
at least 100 ms (t
RPU
) to ensure a robust system reset
at a reliable V
DD
level. After t
RPU
has been met, the
/RST pin will return to the weak high state. While
/RST is asserted, serial bus activity is locked out even
if a transaction occurred as V
DD
dropped below V
TP
.
A memory operation started while V
DD
is above V
TP
will be completed internally.
Figure 2 below illustrates the reset operation in
response to the V
DD
voltage.
VDD
VTP
t
RPU
Memory Operation
The FM3127x is a family of products available in
different memory sizes including 4Kb, 16Kb, 64Kb,
and 256Kb. The family is software compatible, all
versions use consistent two-byte addressing for the
memory device. This makes the lowest density
device different from its stand-alone memory
counterparts but makes them compatible within the
entire family.
Memory is organized in bytes, for example the 4Kb
memory is 512 x 8 and the 256Kb memory is 32,768
x 8. The memory is based on F-RAM technology.
Therefore it can be treated as RAM and is read or
written at the speed of the two-wire bus with no
delays for write operations. It also offers effectively
unlimited write endurance unlike other nonvolatile
memory technologies. The 2-wire interface protocol
is described further on page 13.
The memory array can be write-protected by
software. Two bits in the processor companion area
(WP0, WP1 in register 0Bh) control the protection
setting as shown in the following table. Based on the
setting, the protected addresses cannot be written and
the 2-wire interface will not acknowledge any data to
Rev. 2.0
Dec. 2007
RST
Figure 2. Low Voltage Reset
The bit VTP controls the trip point of the low voltage
detect circuit. It is located in register 0Bh, bit 0. Note
that the bit 1 location is a “don’t care”.
Page 4 of 25
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