FM32278/276/274/272 - 5V I2C Companion
The voltage on the PFI input pin is compared to an
onboard 1.2V reference. When the PFI input voltage
drops below this threshold, the comparator will drive
the PFO pin to a low state. The comparator has 100
mV (max) of hysteresis to reduce noise sensitivity,
only for a rising PFI signal. For a falling PFI edge,
there is no hysteresis.
The comparator is a general purpose device and its
application is not limited to the NMI function.
Note: The maximum voltage on the comparator input PFI
is limited to 3.75V under normal operating conditions.
Serial Number
A memory location to write a 64-bit serial number is
provided. It is a writeable nonvolatile memory block
that can be locked by the user once the serial number
is set. The 8 bytes of data and the lock bit are all
accessed via the device ID for the processor
companion. Therefore the serial number area is
separate and distinct from the memory array. The
serial number registers can be written an unlimited
number of times, so these locations are general
purpose memory.
However once the lock bit is set the
values cannot be altered and the lock cannot be
removed.
Once locked the serial number registers can
still be read by the system.
The serial number is located in registers 11h to 18h.
The lock bit is SNL, register 0Bh bit 7. Setting the
SNL bit to a 1 disables writes to the serial number
registers, and
the SNL bit cannot be cleared.
Backup Power
The event counter and battery-backed registers may
be powered with a backup power source. When the
primary system power fails, the voltage on the V
DD
pin will drop. When V
DD
is less than 2.5V, the event
counters and battery-backed registers will switch to
the backup power supply on V
BAK
.
A battery may be inserted into a system board
without any concern for excessive current draw on
the FM3227x’s V
BAK
pin.
Trickle Charger
To facilitate capacitor backup, the V
BAK
pin can
optionally provide a trickle charge current. When the
VBC bit, register 0Bh bit 2, is set to ‘1’, the V
BAK
pin
will source approximately 80 µA until V
BAK
reaches
3.75V. In 5V systems, this charges the capacitor to
V
DD
without an external diode and resistor charger
and also prevents the user from exceeding the V
BAK
maximum voltage specification. There is a Fast
Charge mode which is enabled by the FC bit (register
0Bh, bit 5). In this mode the trickle charger current is
set to approximately 1 mA, allowing a large backup
capacitor to charge more quickly.
In the case where no backup source is used, the V
BAK
pin should be tied to V
SS
. V
BAK
should not be tied to
5V since the V
BAK
(max) specification will be
exceeded. Be sure to turn off the trickle charger
(VBC=0), otherwise charger current will be shunted
to ground from V
DD
.
!
Note: systems using lithium batteries should clear the
VBC bit to 0 to prevent battery charging. The V
BAK
circuitry includes an internal 1 K
Ω
series resistor as a
safety element. The trickle charger is UL Recognized.
Event Counter
The FM3227x offers the user two battery-backed
event counters. Input pins CNT1 and CNT2 are
programmable edge detectors. Each clocks a 16-bit
counter. When an edge occurs, the counters will
increment their respective registers. Counter 1 is
located in registers 0Dh and 0Eh, Counter 2 is
located in registers 0Fh and 10h. These register
values can be read anytime VDD is above VTP, and
they will be incremented as long as a valid VBAK
power source is provided. To read, set the RC bit
register 0Ch bit 3 to 1. This takes a snapshot of all
four counter bytes allowing a stable value even if a
count occurs during the read. The registers can be
written by software allowing the counters to be
cleared or initialized by the system. Counts are
blocked during a write operation. The two counters
can be cascaded to create a single 32-bit counter by
setting the CC control bit (register 0Ch). When
cascaded, the CNT1 input will cause the counter to
increment. CNT2 is not used in this mode.
C1P
16-bit Counter
CNT1
C2P
CNT2
CC
16-bit Counter
Figure 6. Event Counter
The control bits for event counting are located in
register 0Ch. Counter 1 Polarity is bit C1P, bit 0;
Counter 2 Polarity is C2P, bit 1; the Cascade Control
is CC, bit 2; and the Read Counter bit is RC bit 3.
The polarity bits must be set prior to setting the
counter value(s). If a polarity bit is changed, the
counter may inadvertently increment. If the counter
pins are not being used, tie them to ground.
Rev. 3.0
Feb. 2009
Page 6 of 21
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
