PRODUCT SPECIFICATION
RC5041
Two MOSFETs in Parallel
For high current requirements, we recommend that two
MOSFETs be used in parallel instead of one single MOS-
FET. Significant advantages are realized using two MOS-
FETs in parallel:
•
Significant reduction of power dissipation.
Maximum current of 14A with one MOSFET:
P
MOSFET
=
R
DS(ON)
)(Duty Cycle)
= (14)
2
(0.050
*
)(3.3+0.4)/(5+0.4-0.35)
= 7.2 W
With two MOSFETs in parallel:
R
DS(ON)
)(Duty Cycle)
P
MOSFET
=
= (14/2)
2
(0.037*)(3.3+0.4)/(5+0.4-0.35)
= 1.3W/FET
*Note: R
DS(on)
increases with temperature. Assume R
DS(on)
= 0.025 at
25°C. R
DS(on)
can easily increase to 0.050W at high temperature when
using a single MOSFET. When using two MOSFETs in parallel, the
temperature effects should not cause the R
DS(on)
to rise above the listed
maximum value of 37mW.
PWM/PFM
Control
DS1
+5V
DS2
VCCQP
M
HIDRV
CP
L1
RS
VO
CB
(I
2
65-5041-07
Figure 5. Charge Pump Configuration
Method 2. 12V Gate Bias
(I
2
Preliminary Information
+5V
+12V
47Ω
DS2
6.2V
VCCQP
M1
HIDRV
L1
PWM/PFM
Control
DS1
RS
VO
CB
•
Less heat sink required.
With power dissipation down to around one watt and with
MOSFETs mounted flat on the motherboard, there will be
considerably less heat sink required. The junction-to-case
thermal resistance for the MOSFET package (TO-220) is
typically at 2°C/W and the motherboard serves as an
excellent heat sink.
•
Higher current capability.
With thermal management under control, this on-board
DC-DC converter is able to deliver load currents up to
14.5A with no problem at all.
65-5041-08
Figure 6. 12V Gate Bias Configuration
MOSFET Gate Bias
The MOSFET can be biased by one of two methods: Charge
Pump and 12V Gate Bias.
Method 1. Charge pump (or Bootstrap) method
Figure 7 uses an external 12V source to bias VCCQP. A 47Ω
resistor is used to limit the transient current into the VCCQP
pin. A 1µF capacitor filter is used to filter the VCCQP sup-
ply. This method provides a higher gate bias voltage to the
MOSFET, and therefore reduces the R
SD(ON)
and resulting
power loss within the MOSFET. Figure 8 illustrates how
R
DS(ON)
decreases dramatically as V
GS
increases. A 6.2V
Zener (DS2) is used to clamp the voltage at V
CCQP
to a
maximum of 12V and ensure that the absolute maximum
voltage of the IC will not be exceeded.
0.1
0.09
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0
1.5 2
2.5 3
3.5 4
5
6
7
8
9
V
GS
Figure 5 employs a charge pump to provide gate bias. Capac-
itor CP is the charge pump deployed to boost the voltage of
the RC5041 output driver. When the MOSFET switches off,
the source of the MOSFET is at -0.6V. VCCQP is charged
through the Schottky diode to 4.5V. Thus, the capacitor CP is
charged to 5V. When the MOSFET turns on, the source of
the MOSFET voltage is equal to 5V. The capacitor voltage
follows, and hence provides a voltage at VCCQP equal to
10V. The Schottky is required to provide the charge path
when the MOSFET is off. The Schottky reverses bias when
the VCCQP goes to 10V. The charge pump capacitor, CP,
needs to be a high Q and high frequency capacitor. A 1µF
ceramic capacitor is recommended here.
R
DS(ON)
Ω
10 11
Figure 7. R(DS) vs. V
GS
for Typical MOSFETs
65-5041-09
9
RAYTHEON [ RAYTHEON COMPANY ]
